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tiva/cc13x2_cc26x2: Fix nxstyle errors

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arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_fcfg1.h:

    * Fix nxstyle errors.
This commit is contained in:
Nathan Hartman 2020-11-06 16:41:33 -05:00 committed by Alan Carvalho de Assis
parent f052a9b1e6
commit 94a10033e0
1 changed files with 72 additions and 44 deletions
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68
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_fcfg1.h
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@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_fcfg1.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible BSD
* license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_FCFG1_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_FCFG1_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* FCFG1 Register Offsets *******************************************************************************************/
/* FCFG1 Register Offsets ***************************************************/
#define TIVA_FCFG1_MISC_CONF_1_OFFSET 0x00a0 /* Misc configurations */
#define TIVA_FCFG1_MISC_CONF_2_OFFSET 0x00a4
@ -137,7 +138,7 @@
#define TIVA_FCFG1_DAC_CAL2_OFFSET 0x0428
#define TIVA_FCFG1_DAC_CAL3_OFFSET 0x042c
/* FCFG1 Register Register Addresses ********************************************************************************/
/* FCFG1 Register Register Addresses ****************************************/
#define TIVA_FCFG1_MISC_CONF_1 (TIVA_FCFG1_BASE + TIVA_FCFG1_MISC_CONF_1_OFFSET)
#define TIVA_FCFG1_MISC_CONF_2 (TIVA_FCFG1_BASE + TIVA_FCFG1_MISC_CONF_2_OFFSET)
@ -222,7 +223,7 @@
#define TIVA_FCFG1_DAC_CAL2 (TIVA_FCFG1_BASE + TIVA_FCFG1_DAC_CAL2_OFFSET)
#define TIVA_FCFG1_DAC_CAL3 (TIVA_FCFG1_BASE + TIVA_FCFG1_DAC_CAL3_OFFSET)
/* FCFG1 Bitfield Definitions ***************************************************************************************/
/* FCFG1 Bitfield Definitions ***********************************************/
/* TIVA_FCFG1_MISC_CONF_1 */
@ -478,7 +479,9 @@
#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_MASK (15 << FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_SHIFT)
# define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM(n) ((uint32_t)(n) << FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_SHIFT)
/* TIVA_FCFG1_FLASH_NUMBER (32-bit value, Number of the manufacturing lot that produced this unit.) */
/* TIVA_FCFG1_FLASH_NUMBER (32-bit value, Number of the manufacturing lot
* that produced this unit.)
*/
/* TIVA_FCFG1_FLASH_COORDINATE */
@ -718,10 +721,21 @@
#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_MASK (31 << FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_SHIFT)
# define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP(n) ((uint32_t)(n) << FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_SHIFT)
/* TIVA_FCFG1_MAC_BLE_0 (32-bit value, The first 32-bits of the 64-bit MAC BLE address) */
/* TIVA_FCFG1_MAC_BLE_1 (32-bit value, The last 32-bits of the 64-bit MAC BLE address) */
/* TIVA_FCFG1_MAC_15_4_0 (32-bit value, The first 32-bits of the 64-bit MAC 15.4 address) */
/* TIVA_FCFG1_MAC_15_4_1 (32-bit value, The last 32-bits of the 64-bit MAC 15.4 address) */
/* TIVA_FCFG1_MAC_BLE_0 (32-bit value, The first 32-bits of the 64-bit
* MAC BLE address)
*/
/* TIVA_FCFG1_MAC_BLE_1 (32-bit value, The last 32-bits of the 64-bit
* MAC BLE address)
*/
/* TIVA_FCFG1_MAC_15_4_0 (32-bit value, The first 32-bits of the 64-bit
* MAC 15.4 address)
*/
/* TIVA_FCFG1_MAC_15_4_1 (32-bit value, The last 32-bits of the 64-bit
* MAC 15.4 address)
*/
/* TIVA_FCFG1_FLASH_OTP_DATA4 */
@ -802,7 +816,9 @@ degrees C */
#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_MASK (15 << FCFG1_ICEPICK_DEVICE_ID_PG_REV_SHIFT)
# define FCFG1_ICEPICK_DEVICE_ID_PG_REV(n) ((uint32_t)(n) << FCFG1_ICEPICK_DEVICE_ID_PG_REV_SHIFT)
/* TIVA_FCFG1_FCFG1_REVISION (32-bit value, The revision number of the FCFG1 layout) */
/* TIVA_FCFG1_FCFG1_REVISION (32-bit value, The revision number of the
* FCFG1 layout)
*/
/* TIVA_FCFG1_MISC_OTP_DATA */
@ -1157,10 +1173,21 @@ degrees C */
#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_MASK (0xff << FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_SHIFT)
# define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF(n) ((uint32_t)(n) << FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_SHIFT)
/* TIVA_FCFG1_SHDW_DIE_ID_0 (32-bit value, Shadow of DIE_ID_0 register in eFuse row number 5) */
/* TIVA_FCFG1_SHDW_DIE_ID_1 (32-bit value, Shadow of DIE_ID_1 register in eFuse row number 6) */
/* TIVA_FCFG1_SHDW_DIE_ID_2 (32-bit value, Shadow of DIE_ID_2 register in eFuse row number 7) */
/* TIVA_FCFG1_SHDW_DIE_ID_3 (32-bit value, Shadow of DIE_ID_3 register in eFuse row number 8) */
/* TIVA_FCFG1_SHDW_DIE_ID_0 (32-bit value, Shadow of DIE_ID_0 register
* in eFuse row number 5)
*/
/* TIVA_FCFG1_SHDW_DIE_ID_1 (32-bit value, Shadow of DIE_ID_1 register
* in eFuse row number 6)
*/
/* TIVA_FCFG1_SHDW_DIE_ID_2 (32-bit value, Shadow of DIE_ID_2 register
* in eFuse row number 7)
*/
/* TIVA_FCFG1_SHDW_DIE_ID_3 (32-bit value, Shadow of DIE_ID_3 register
* in eFuse row number 8)
*/
/* TIVA_FCFG1_SHDW_OSC_BIAS_LDO_TRIM */
@ -1218,6 +1245,7 @@ degrees C */
# define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT(n) ((uint32_t)(n) << FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_SHIFT)
/* TIVA_FCFG1_TFW_PROBE (32-bit value) */
/* TIVA_FCFG1_TFW_FT (32-bit value) */
/* TIVA_FCFG1_DAC_CAL0 */