SAMA5D2: Add PIO register definition header file
This commit is contained in:
Gregory Nutt
parent
b8c1f0bfeb
commit
94bdeda28e
54
arch/arm/src/sama5/chip/sam_pio.h
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54
arch/arm/src/sama5/chip/sam_pio.h
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/************************************************************************************
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* arch/arm/src/sama5/chip/sam_pio.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIO_H
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#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIO_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/sama5/chip.h>
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#if defined(ATSAMA5D2)
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# include "chip/sama5d2x_pio.h"
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#elif defined(ATSAMA5D3) || defined(ATSAMA5D4)
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# include "chip/sama5d3x4x_pio.h"
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#else
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# error Unrecognized SAMA5 architecture
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#endif
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIO_H */
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@ -172,15 +172,7 @@
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# define SAM_UDPHS_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: UDPHS */
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# define SAM_ADC_OFFSET 0x00030000 /* 0x00030000-0x00033fff: ADC */
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/* 0x00034000-0x00037fff: Reserved */
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# define SAM_PIO_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: PIO */
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# define SAM_PIOA_OFFSET 0x00038000 /* 0x00038000-0x0003803f: PIOA */
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# define SAM_PIOB_OFFSET 0x00038040 /* 0x00038040-0x0003807f: PIOB */
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# define SAM_PIOC_OFFSET 0x00038080 /* 0x00038080-0x000380bf: PIOC */
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# define SAM_PIOD_OFFSET 0x000380c0 /* 0x000380c0-0x000380ff: PIOD */
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# define SAM_SPIOA_OFFSET 0x00039000 /* 0x00039000-0x0003903f: Secure PIOA */
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# define SAM_SPIOB_OFFSET 0x00039040 /* 0x00039040-0x0003907f: Secure PIOB */
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# define SAM_SPIOC_OFFSET 0x00039080 /* 0x00039080-0x000390bf: Secure PIOC */
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# define SAM_SPIOD_OFFSET 0x000390c0 /* 0x000390c0-0x000390ff: Secure PIOD */
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# define SAM_PIO_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: PIOA-D */
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# define SAM_MATRIX1_OFFSET 0x0003c000 /* 0x0003c000-0x0003ffff: MATRIX1 */
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# define SAM_SECUMOD_OFFSET 0x00040000 /* 0x00040000-0x00043fff: SECUMOD */
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# define SAM_TDES_OFFSET 0x00044000 /* 0x00044000-0x00047fff: TDES */
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@ -519,14 +511,6 @@
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#define SAM_UDPHS_VBASE (SAM_PERIPHC_VSECTION+SAM_UDPHS_OFFSET)
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#define SAM_ADC_VBASE (SAM_PERIPHC_VSECTION+SAM_ADC_OFFSET)
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#define SAM_PIO_VBASE (SAM_PERIPHC_VSECTION+SAM_PIO_OFFSET)
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# define SAM_PIOA_VBASE (SAM_PERIPHC_VSECTION+SAM_PIOA_OFFSET)
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# define SAM_PIOB_VBASE (SAM_PERIPHC_VSECTION+SAM_PIOB_OFFSET)
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# define SAM_PIOC_VBASE (SAM_PERIPHC_VSECTION+SAM_PIOC_OFFSET)
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# define SAM_PIOD_VBASE (SAM_PERIPHC_VSECTION+SAM_PIOD_OFFSET)
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# define SAM_SPIOA_VBASE (SAM_PERIPHC_VSECTION+SAM_SPIOA_OFFSET)
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# define SAM_SPIOB_VBASE (SAM_PERIPHC_VSECTION+SAM_SPIOB_OFFSET)
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# define SAM_SPIOC_VBASE (SAM_PERIPHC_VSECTION+SAM_SPIOC_OFFSET)
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# define SAM_SPIOD_VBASE (SAM_PERIPHC_VSECTION+SAM_SPIOD_OFFSET)
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#define SAM_MATRIX1_VBASE (SAM_PERIPHC_VSECTION+SAM_MATRIX1_OFFSET)
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#define SAM_SECUMOD_VBASE (SAM_PERIPHC_VSECTION+SAM_SECUMOD_OFFSET)
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#define SAM_TDES_VBASE (SAM_PERIPHC_VSECTION+SAM_TDES_OFFSET)
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336
arch/arm/src/sama5/chip/sama5d2x_pio.h
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336
arch/arm/src/sama5/chip/sama5d2x_pio.h
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@ -0,0 +1,336 @@
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/****************************************************************************************
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* arch/arm/src/samv7/chip/sama5d2x_pio.h
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* Parallel Input/Output (PIO) Controller definitions for the SAMA5D2
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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||||
* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAMA5D2X_PIO_H
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#define __ARCH_ARM_SRC_SAMA5_CHIP_SAMA5D2X_PIO_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* Misc Helper Definitions **************************************************************/
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#define PIOA (0)
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#define PIOB (1)
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#define PIOC (2)
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#define PIOD (3)
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#define PIOE (4)
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/* PIO register offsets *****************************************************************/
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#define SAM_PIO_IOGROUP_OFFSET(n) (0x0000 + ((n) << 6))
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# define SAM_PIO_IOGROUPA_OFFSET 0x0000
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# define SAM_PIO_IOGROUPB_OFFSET 0x0040
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# define SAM_PIO_IOGROUPC_OFFSET 0x0080
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# define SAM_PIO_IOGROUPD_OFFSET 0x00c0
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#define SAM_PIO_MSKR_OFFSET 0x0000 /* PIO Mask Register */
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#define SAM_PIO_CFGR_OFFSET 0x0004 /* PIO Configuration Register */
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#define SAM_PIO_PDS_OFFSET 0x0008 /* PIO Pin Data Status Register */
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#define SAM_PIO_LOCKSR_OFFSET 0x000c /* PIO Lock Status Register */
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#define SAM_PIO_SODR_OFFSET 0x0010 /* PIO Set Output Data Register */
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#define SAM_PIO_CODR_OFFSET 0x0014 /* PIO Clear Output Data Register */
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#define SAM_PIO_ODSR_OFFSET 0x0018 /* PIO Output Data Status Register */
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/* 0x001c: Reserved */
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#define SAM_PIO_IER_OFFSET 0x0020 /* PIO Interrupt Enable Register */
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#define SAM_PIO_IDR_OFFSET 0x0024 /* PIO Interrupt Disable Register */
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#define SAM_PIO_IMR_OFFSET 0x0028 /* PIO Interrupt Mask Register */
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#define SAM_PIO_ISR_OFFSET 0x002c /* PIO Interrupt Status Register */
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/* 0x0030-0x0038: Reserved */
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#define SAM_PIO_IOFR_OFFSET 0x003c /* PIO I/O Freeze Register */
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/* 0x0040-0x05dc: Reserved */
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#define SAM_PIO_WPMR_OFFSET 0x05e0 /* PIO Write Protection Mode Register */
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#define SAM_PIO_WPSR_OFFSET 0x05e4 /* PIO Write Protection Status Register */
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/* 0x05e8–0x0ffc: Reserved */
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#define SAM_SPIO_IOGROUP_OFFSET(n) (0x1000 + ((n) << 6))
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# define SAM_SPIO_IOGROUPA_OFFSET 0x1000
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# define SAM_SPIO_IOGROUPB_OFFSET 0x1040
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# define SAM_SPIO_IOGROUPC_OFFSET 0x1080
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# define SAM_SPIO_IOGROUPD_OFFSET 0x10c0
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#define SAM_SPIO_MSKR_OFFSET 0x0000 /* Secure PIO Mask Register */
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#define SAM_SPIO_CFGR_OFFSET 0x0004 /* Secure PIO Configuration Register */
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#define SAM_SPIO_PDSR_OFFSET 0x0008 /* Secure PIO Pin Data Status Register */
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#define SAM_SPIO_LOCKSR_OFFSET 0x000c /* Secure PIO Lock Status Register */
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#define SAM_SPIO_SODR_OFFSET 0x0010 /* Secure PIO Set Output Data Register */
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#define SAM_SPIO_CODR_OFFSET 0x0014 /* Secure PIO Clear Output Data Register */
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#define SAM_SPIO_ODSR_OFFSET 0x0018 /* Secure PIO Output Data Status Register */
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/* 0x001c: Reserved */
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#define SAM_SPIO_IER_OFFSET 0x0020 /* Secure PIO Interrupt Enable Register */
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#define SAM_SPIO_IDR_OFFSET 0x0024 /* Secure PIO Interrupt Disable Register */
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#define SAM_SPIO_IMR_OFFSET 0x0028 /* Secure PIO Interrupt Mask Register */
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#define SAM_SPIO_ISR_OFFSET 0x002c /* Secure PIO Interrupt Status Register */
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#define SAM_SPIO_SIONR_OFFSET 0x0030 /* Secure PIO Set I/O Non-Secure Register */
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#define SAM_SPIO_SIOSR_OFFSET 0x0034 /* Secure PIO Set I/O Secure Register */
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#define SAM_SPIO_IOSSR_OFFSET 0x0038 /* Secure PIO I/O Security Status Register */
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#define SAM_SPIO_IOFR_OFFSET 0x003c /* Secure PIO I/O Freeze Register */
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/* 0x1400–0x14fc: Reserved */
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#define SAM_SPIO_SCDR_OFFSET 0x1500 /* Secure PIO Slow Clock Divider Debouncing Register */
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/* 0x1504-0x15dc: Reserved */
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#define SAM_SPIO_WPMR_OFFSET 0x15e0 /* Secure PIO Write Protection Mode Register */
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#define SAM_SPIO_WPSR_OFFSET 0x15e4 /* Secure PIO Write Protection Status Register */
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/* PIO register addresses ***************************************************************/
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#define SAM_PIO_IOGROUP_VBASE(n) (SAM_PIO_VBASE+SAM_PIO_IOGROUP_OFFSET(n))
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# define SAM_PIO_IOGROUPA_VBASE (SAM_PIO_VBASE+SAM_PIO_IOGROUPA_OFFSET)
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# define SAM_PIO_IOGROUPB_VBASE (SAM_PIO_VBASE+SAM_PIO_IOGROUPB_OFFSET)
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# define SAM_PIO_IOGROUPC_VBASE (SAM_PIO_VBASE+SAM_PIO_IOGROUPC_OFFSET)
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# define SAM_PIO_IOGROUPD_VBASE (SAM_PIO_VBASE+SAM_PIO_IOGROUPD_OFFSET)
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#define SAM_PIOA_MSKR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_MSKR_OFFSET)
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#define SAM_PIOA_CFGR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_CFGR_OFFSET)
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#define SAM_PIOA_PDS (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_PDS_OFFSET)
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#define SAM_PIOA_LOCKSR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_LOCKSR_OFFSET)
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#define SAM_PIOA_SODR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_SODR_OFFSET)
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#define SAM_PIOA_CODR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_CODR_OFFSET)
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#define SAM_PIOA_ODSR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_ODSR_OFFSET)
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#define SAM_PIOA_IER (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_IER_OFFSET)
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#define SAM_PIOA_IDR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_IDR_OFFSET)
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#define SAM_PIOA_IMR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_IMR_OFFSET)
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#define SAM_PIOA_ISR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_ISR_OFFSET)
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#define SAM_PIOA_IOFR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_IOFR_OFFSET)
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#define SAM_PIOB_MSKR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_MSKR_OFFSET)
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#define SAM_PIOB_CFGR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_CFGR_OFFSET)
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#define SAM_PIOB_PDS (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_PDS_OFFSET)
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#define SAM_PIOB_LOCKSR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_LOCKSR_OFFSET)
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#define SAM_PIOB_SODR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_SODR_OFFSET)
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#define SAM_PIOB_CODR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_CODR_OFFSET)
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#define SAM_PIOB_ODSR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_ODSR_OFFSET)
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#define SAM_PIOB_IER (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_IER_OFFSET)
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#define SAM_PIOB_IDR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_IDR_OFFSET)
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#define SAM_PIOB_IMR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_IMR_OFFSET)
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#define SAM_PIOB_ISR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_ISR_OFFSET)
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#define SAM_PIOB_IOFR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_IOFR_OFFSET)
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#define SAM_PIOC_MSKR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_MSKR_OFFSET)
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#define SAM_PIOC_CFGR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_CFGR_OFFSET)
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#define SAM_PIOC_PDS (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_PDS_OFFSET)
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#define SAM_PIOC_LOCKSR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_LOCKSR_OFFSET)
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#define SAM_PIOC_SODR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_SODR_OFFSET)
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#define SAM_PIOC_CODR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_CODR_OFFSET)
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#define SAM_PIOC_ODSR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_ODSR_OFFSET)
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#define SAM_PIOC_IER (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_IER_OFFSET)
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#define SAM_PIOC_IDR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_IDR_OFFSET)
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#define SAM_PIOC_IMR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_IMR_OFFSET)
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#define SAM_PIOC_ISR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_ISR_OFFSET)
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#define SAM_PIOC_IOFR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_IOFR_OFFSET)
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#define SAM_PIOD_MSKR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_MSKR_OFFSET)
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#define SAM_PIOD_CFGR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_CFGR_OFFSET)
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#define SAM_PIOD_PDS (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_PDS_OFFSET)
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#define SAM_PIOD_LOCKSR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_LOCKSR_OFFSET)
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#define SAM_PIOD_SODR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_SODR_OFFSET)
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#define SAM_PIOD_CODR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_CODR_OFFSET)
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#define SAM_PIOD_ODSR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_ODSR_OFFSET)
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#define SAM_PIOD_IER (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_IER_OFFSET)
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#define SAM_PIOD_IDR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_IDR_OFFSET)
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#define SAM_PIOD_IMR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_IMR_OFFSET)
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#define SAM_PIOD_ISR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_ISR_OFFSET)
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#define SAM_PIOD_IOFR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_IOFR_OFFSET)
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#define SAM_PIO_WPMR (SAM_PIO_VBASE+SAM_PIO_WPMR_OFFSET)
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#define SAM_PIO_WPSR (SAM_PIO_VBASE+SAM_PIO_WPSR_OFFSET)
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#define SAM_SPIO_IOGROUP_VBASE(n) (SAM_PIO_VBASE+SAM_SPIO_IOGROUP_OFFSET(n))
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# define SAM_SPIO_IOGROUPA_VBASE (SAM_PIO_VBASE+SAM_SPIO_IOGROUPA_OFFSET)
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# define SAM_SPIO_IOGROUPB_VBASE (SAM_PIO_VBASE+SAM_SPIO_IOGROUPB_OFFSET)
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# define SAM_SPIO_IOGROUPC_VBASE (SAM_PIO_VBASE+SAM_SPIO_IOGROUPC_OFFSET)
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# define SAM_SPIO_IOGROUPD_VBASE (SAM_PIO_VBASE+SAM_SPIO_IOGROUPD_OFFSET)
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#define SAM_SPIOA_MSKR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_MSKR_OFFSET)
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#define SAM_SPIOA_CFGR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_CFGR_OFFSET)
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#define SAM_SPIOA_PDSR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_PDSR_OFFSET)
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#define SAM_SPIOA_LOCKSR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_LOCKSR_OFFSET)
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#define SAM_SPIOA_SODR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_SODR_OFFSET)
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#define SAM_SPIOA_CODR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_CODR_OFFSET)
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#define SAM_SPIOA_ODSR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_ODSR_OFFSET)
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#define SAM_SPIOA_IER (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_IER_OFFSET)
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#define SAM_SPIOA_IDR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_IDR_OFFSET)
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#define SAM_SPIOA_IMR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_IMR_OFFSET)
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#define SAM_SPIOA_ISR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_ISR_OFFSET)
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#define SAM_SPIOA_SIONR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_SIONR_OFFSET)
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#define SAM_SPIOA_SIOSR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_SIOSR_OFFSET)
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#define SAM_SPIOA_IOSSR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_IOSSR_OFFSET)
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#define SAM_SPIOA_IOFR (SAM_PIO_IOGROUPA_VBASE+SAM_SPIO_IOFR_OFFSET)
|
||||
|
||||
#define SAM_SPIOB_MSKR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_MSKR_OFFSET)
|
||||
#define SAM_SPIOB_CFGR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_CFGR_OFFSET)
|
||||
#define SAM_SPIOB_PDSR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_PDSR_OFFSET)
|
||||
#define SAM_SPIOB_LOCKSR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_LOCKSR_OFFSET)
|
||||
#define SAM_SPIOB_SODR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_SODR_OFFSET)
|
||||
#define SAM_SPIOB_CODR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_CODR_OFFSET)
|
||||
#define SAM_SPIOB_ODSR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_ODSR_OFFSET)
|
||||
#define SAM_SPIOB_IER (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_IER_OFFSET)
|
||||
#define SAM_SPIOB_IDR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_IDR_OFFSET)
|
||||
#define SAM_SPIOB_IMR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_IMR_OFFSET)
|
||||
#define SAM_SPIOB_ISR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_ISR_OFFSET)
|
||||
#define SAM_SPIOB_SIONR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_SIONR_OFFSET)
|
||||
#define SAM_SPIOB_SIOSR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_SIOSR_OFFSET)
|
||||
#define SAM_SPIOB_IOSSR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_IOSSR_OFFSET)
|
||||
#define SAM_SPIOB_IOFR (SAM_PIO_IOGROUPB_VBASE+SAM_SPIO_IOFR_OFFSET)
|
||||
|
||||
#define SAM_SPIOC_MSKR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_MSKR_OFFSET)
|
||||
#define SAM_SPIOC_CFGR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_CFGR_OFFSET)
|
||||
#define SAM_SPIOC_PDSR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_PDSR_OFFSET)
|
||||
#define SAM_SPIOC_LOCKSR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_LOCKSR_OFFSET)
|
||||
#define SAM_SPIOC_SODR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_SODR_OFFSET)
|
||||
#define SAM_SPIOC_CODR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_CODR_OFFSET)
|
||||
#define SAM_SPIOC_ODSR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_ODSR_OFFSET)
|
||||
#define SAM_SPIOC_IER (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_IER_OFFSET)
|
||||
#define SAM_SPIOC_IDR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_IDR_OFFSET)
|
||||
#define SAM_SPIOC_IMR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_IMR_OFFSET)
|
||||
#define SAM_SPIOC_ISR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_ISR_OFFSET)
|
||||
#define SAM_SPIOC_SIONR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_SIONR_OFFSET)
|
||||
#define SAM_SPIOC_SIOSR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_SIOSR_OFFSET)
|
||||
#define SAM_SPIOC_IOSSR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_IOSSR_OFFSET)
|
||||
#define SAM_SPIOC_IOFR (SAM_PIO_IOGROUPC_VBASE+SAM_SPIO_IOFR_OFFSET)
|
||||
|
||||
#define SAM_SPIOD_MSKR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_MSKR_OFFSET)
|
||||
#define SAM_SPIOD_CFGR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_CFGR_OFFSET)
|
||||
#define SAM_SPIOD_PDSR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_PDSR_OFFSET)
|
||||
#define SAM_SPIOD_LOCKSR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_LOCKSR_OFFSET)
|
||||
#define SAM_SPIOD_SODR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_SODR_OFFSET)
|
||||
#define SAM_SPIOD_CODR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_CODR_OFFSET)
|
||||
#define SAM_SPIOD_ODSR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_ODSR_OFFSET)
|
||||
#define SAM_SPIOD_IER (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_IER_OFFSET)
|
||||
#define SAM_SPIOD_IDR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_IDR_OFFSET)
|
||||
#define SAM_SPIOD_IMR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_IMR_OFFSET)
|
||||
#define SAM_SPIOD_ISR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_ISR_OFFSET)
|
||||
#define SAM_SPIOD_SIONR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_SIONR_OFFSET)
|
||||
#define SAM_SPIOD_SIOSR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_SIOSR_OFFSET)
|
||||
#define SAM_SPIOD_IOSSR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_IOSSR_OFFSET)
|
||||
#define SAM_SPIOD_IOFR (SAM_PIO_IOGROUPD_VBASE+SAM_SPIO_IOFR_OFFSET)
|
||||
|
||||
#define SAM_SPIO_SCDR (SAM_PIO_VBASE+SAM_SPIO_SCDR_OFFSET)
|
||||
#define SAM_SPIO_WPMR (SAM_PIO_VBASE+SAM_SPIO_WPMR_OFFSET)
|
||||
#define SAM_SPIO_WPSR (SAM_PIO_VBASE+SAM_SPIO_WPSR_OFFSET)
|
||||
|
||||
/* PIO register bit definitions *********************************************************/
|
||||
|
||||
/* Common bit definitions for many IO registers (exceptions follow) */
|
||||
|
||||
#define PIO(n) (1 << (n)) /* Bit n: PIO n, n=0-31 */
|
||||
|
||||
/* PIO Configuration Register and Secure PIO Configuration Register */
|
||||
|
||||
#define PIO_CFGR_FUNC_SHIFT (0) /* Bits 0-2: I/O Line Function */
|
||||
#define PIO_CFGR_FUNC_MASK (7 << PIO_CFGR_FUNC_SHIFT)
|
||||
# define PIO_CFGR_FUNC_GPIO (0 << PIO_CFGR_FUNC_SHIFT) /* Select PIO mode */
|
||||
# define PIO_CFGR_FUNC_PERIPH(n) ((uint32_t)((n)+1) << PIO_CFGR_FUNC_SHIFT)
|
||||
# define PIO_CFGR_FUNC_PERIPHA (1 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral A */
|
||||
# define PIO_CFGR_FUNC_PERIPHB (2 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral B */
|
||||
# define PIO_CFGR_FUNC_PERIPHC (3 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral C */
|
||||
# define PIO_CFGR_FUNC_PERIPHD (4 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral D */
|
||||
# define PIO_CFGR_FUNC_PERIPHE (5 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral E */
|
||||
# define PIO_CFGR_FUNC_PERIPHF (6 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral F */
|
||||
# define PIO_CFGR_FUNC_PERIPHG (7 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral G */
|
||||
#define PIO_CFGR_DIR (1 << 8) /* Bit 8: Direction */
|
||||
#define PIO_CFGR_PUEN (1 << 9) /* Bit 9: Pull-Up Enable */
|
||||
#define PIO_CFGR_PDEN (1 << 10) /* Bit 10: Pull-Down Enable */
|
||||
#define PIO_CFGR_IFEN (1 << 12) /* Bit 12: Input Filter Enable */
|
||||
#define PIO_CFGR_IFSCEN (1 << 13) /* Bit 13: Input Filter Slow Clock Enable */
|
||||
#define PIO_CFGR_OPD (1 << 14) /* Bit 14: Open-Drain */
|
||||
#define PIO_CFGR_SCHMITT (1 << 15) /* Bit 15: Schmitt Trigger */
|
||||
#define PIO_CFGR_DRVSTR_SHIFT (16) /* Bits 16-17: Drive Strength */
|
||||
#define PIO_CFGR_DRVSTR_MASK (3 << PIO_CFGR_DRVSTR_SHIFT)
|
||||
# define PIO_CFGR_DRVSTR_LOW (0 << PIO_CFGR_DRVSTR_SHIFT) /* Low drive */
|
||||
# define PIO_CFGR_DRVSTR_MED (2 << PIO_CFGR_DRVSTR_SHIFT) /* Medium drive */
|
||||
# define PIO_CFGR_DRVSTR_HIGH (3 << PIO_CFGR_DRVSTR_SHIFT) /* High drive */
|
||||
#define PIO_CFGR_EVTSEL_SHIFT (24) /* Bits 24-26: Event Selection */
|
||||
#define PIO_CFGR_EVTSEL_MASK (7 << PIO_CFGR_EVTSEL_SHIFT)
|
||||
# define PIO_CFGR_EVTSEL_FALLING (0 << PIO_CFGR_EVTSEL_SHIFT) /* Event detection on input falling edge */
|
||||
# define PIO_CFGR_EVTSEL_RISING (1 << PIO_CFGR_EVTSEL_SHIFT) /* Event detection on input rising edge */
|
||||
# define PIO_CFGR_EVTSEL_BOTH (2 << PIO_CFGR_EVTSEL_SHIFT) /* Event detection on input both edge */
|
||||
# define PIO_CFGR_EVTSEL_LOW (3 << PIO_CFGR_EVTSEL_SHIFT) /* Event detection on low level input */
|
||||
# define PIO_CFGR_EVTSEL_HIGH (4 << PIO_CFGR_EVTSEL_SHIFT) /* Event detection on high level input */
|
||||
#define PIO_CFGR_PCFS (1 << 29) /* Bit 29: Physical Configuration Freeze Status */
|
||||
#define PIO_CFGR_ICFS (1 << 30) /* Bit 30: Interrupt Configuration Freeze Status */
|
||||
|
||||
/* PIO I/O Freeze Register and Secure PIO I/O Freeze Register */
|
||||
|
||||
#define PIO_IOFR_FPHY (1 << 0) /* Bit 0: Freeze Physical Configuration */
|
||||
#define PIO_IOFR_FINT (1 << 1) /* Bit 1: Freeze Interrupt Configuration */
|
||||
#define PIO_IOFR_FRZKEY_SHIFT (8) /* Bits 8-31: Freeze Key */
|
||||
#define PIO_IOFR_FRZKEY_MASK (0x00ffffff << PIO_IOFR_FRZKEY_SHIFT)
|
||||
# define PIO_IOFR_FRZKEY (0x00494F46 << PIO_IOFR_FRZKEY_SHIFT) /* ""IOF" */
|
||||
|
||||
/* PIO Write Protection Mode Register and Secure PIO Write Protection Mode Register */
|
||||
|
||||
#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protection Enable */
|
||||
#define PIO_WPMR_WPITEN (1 << 1) /* Bit 1: Write Protection Interrupt Enable */
|
||||
#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection Key */
|
||||
#define PIO_WPMR_WPKEY_MASK (0x00ffffff << PIO_WPMR_WPKEY_SHIFT)
|
||||
# define PIO_WPMR_WPKEY (0x0050494f << PIO_WPMR_WPKEY_SHIFT) /* "PIO" */
|
||||
|
||||
/* PIO Write Protection Status Register and Secure PIO Write Protection Status Register*/
|
||||
|
||||
#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protection Violation Status */
|
||||
#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
|
||||
#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT)
|
||||
|
||||
/* Secure PIO Slow Clock Divider Debouncing Register */
|
||||
|
||||
#define SPIO_SCDR_DIV_SHIFT (0) /* Bits 0-13: Slow Clock Divider Selection for Debouncing */
|
||||
#define SPIO_SCDR_DIV_MASK (0x3fff << SPIO_SCDR_DIV_SHIFT)
|
||||
# define SPIO_SCDR_DIV(n) ((uint32_t)(n) << SPIO_SCDR_DIV_SHIFT)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* SAMV7_NPIO > 0 */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAMA5D2X_PIO_H */
|
||||
@ -49,6 +49,13 @@
|
||||
/****************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************/
|
||||
/* Misc Helper Definitions **************************************************************/
|
||||
|
||||
#define PIOA (0)
|
||||
#define PIOB (1)
|
||||
#define PIOC (2)
|
||||
#define PIOD (3)
|
||||
#define PIOE (4)
|
||||
|
||||
/* PIO register offsets *****************************************************************/
|
||||
|
||||
|
||||
@ -73,7 +73,7 @@
|
||||
|
||||
/* 32-bit Encoding:
|
||||
*
|
||||
* .... ...M MMMM CCCC CDDI IISV .PPB BBBB
|
||||
* .... ...M MMMM CCCC CDDI II.V .PPB BBBB
|
||||
*/
|
||||
|
||||
/* Input/Output mode:
|
||||
@ -92,6 +92,7 @@
|
||||
# define PIO_PERIPHD (6 << PIO_MODE_SHIFT) /* Controlled by periph D signal */
|
||||
# define PIO_PERIPHE (7 << PIO_MODE_SHIFT) /* Controlled by periph E signal */
|
||||
# define PIO_PERIPHF (8 << PIO_MODE_SHIFT) /* Controlled by periph F signal */
|
||||
# define PIO_PERIPHG (9 << PIO_MODE_SHIFT) /* Controlled by periph G signal */
|
||||
|
||||
/* These bits set the configuration of the pin:
|
||||
* NOTE: No definitions for parallel capture mode
|
||||
@ -104,7 +105,7 @@
|
||||
# define PIO_CFG_DEFAULT (0 << PIO_CFG_SHIFT) /* Default, no attribute */
|
||||
# define PIO_CFG_PULLUP (1 << PIO_CFG_SHIFT) /* Bit 15: Internal pull-up */
|
||||
# define PIO_CFG_PULLDOWN (2 << PIO_CFG_SHIFT) /* Bit 16: Internal pull-down */
|
||||
# define PIO_CFG_DEGLITCH (4 << PIO_CFG_SHIFT) /* Bit 17: Internal glitch filter */
|
||||
# define PIO_CFG_DEGLITCH (4 << PIO_CFG_SHIFT) /* Bit 17: Internal input filter */
|
||||
# define PIO_CFG_OPENDRAIN (8 << PIO_CFG_SHIFT) /* Bit 18: Open drain */
|
||||
# define PIO_CFG_SCHMITT (16 << PIO_CFG_SHIFT) /* Bit 19: Schmitt trigger */
|
||||
|
||||
@ -126,29 +127,12 @@
|
||||
|
||||
#define PIO_INT_SHIFT (10) /* Bits 9-12: PIO interrupt bits */
|
||||
#define PIO_INT_MASK (7 << PIO_INT_SHIFT)
|
||||
# define _PIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */
|
||||
# define _PIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */
|
||||
# define _PIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
|
||||
# define _PIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */
|
||||
# define _PIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */
|
||||
|
||||
# define PIO_INT_HIGHLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_RH)
|
||||
# define PIO_INT_LOWLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_FL)
|
||||
# define PIO_INT_RISING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_RH)
|
||||
# define PIO_INT_FALLING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_FL)
|
||||
# define PIO_INT_BOTHEDGES (0)
|
||||
|
||||
/* If the pin is an interrupt, then this determines if the pin is a secure interrupt:
|
||||
*
|
||||
* .... .... .... .... .... ..S. .... ....
|
||||
*/
|
||||
|
||||
#ifdef SAMA5_SAIC
|
||||
# define PIO_INT_SECURE (1 << 9) /* Bit 9: Secure interrupt */
|
||||
#else
|
||||
# define PIO_INT_SECURE (0)
|
||||
#endif
|
||||
#define PIO_INT_UNSECURE (0)
|
||||
# define PIO_INT_NONE (0 << PIO_INT_SHIFT)
|
||||
# define PIO_INT_FALLING (1 << PIO_INT_SHIFT)
|
||||
# define PIO_INT_RISING (2 << PIO_INT_SHIFT)
|
||||
# define PIO_INT_BOTHEDGES (3 << PIO_INT_SHIFT)
|
||||
# define PIO_INT_LOWLEVEL (4 << PIO_INT_SHIFT)
|
||||
# define PIO_INT_HIGHLEVEL (5 << PIO_INT_SHIFT)
|
||||
|
||||
/* If the pin is an PIO output, then this identifies the initial output value:
|
||||
*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user