stm32f0l0g0: Add GPIOE to STM32G0x
All STM32G0x series have 6 GPIO ports A to F. Refered: RM0444, RM0454 Signed-off-by: Takumi Ando <t-ando@advaly.co.jp>
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@ -50,7 +50,7 @@
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# define STM32_NDAC 0 /* One DAC channel */
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# define STM32_NCOMP 0 /* Two Analog Comparators */
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# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */
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# define STM32_NPORTS 5 /* Six GPIO ports, GPIOA-F */
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# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F051R8)
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@ -244,7 +244,7 @@
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# define STM32_NCRC 1 /* No CRC module */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \
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defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \
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@ -277,7 +277,7 @@
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# define STM32_NCRC 0 /* No CRC module */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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/* STM32L EnergyLite Line ***************************************************/
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@ -112,6 +112,7 @@
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#define STM32_GPIOB_BASE 0x50000400 /* 0x50000400-0x500007ff: GPIO Port B */
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#define STM32_GPIOC_BASE 0x50000800 /* 0x50000800-0x50000bff: GPIO Port C */
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#define STM32_GPIOD_BASE 0X50000C00 /* 0x50000c00-0x50000fff: GPIO Port D */
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#define STM32_GPIOE_BASE 0X50001000 /* 0x50001000-0x500013ff: GPIO Port E */
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#define STM32_GPIOF_BASE 0x50001400 /* 0x50001400-0x500017ff: GPIO Port F */
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/* Cortex-M4 Base Addresses *************************************************/
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