diff --git a/arch/arm/include/stm32f0l0g0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h
index 31d9f78db9..cba9564d41 100644
--- a/arch/arm/include/stm32f0l0g0/chip.h
+++ b/arch/arm/include/stm32f0l0g0/chip.h
@@ -50,7 +50,7 @@
 #  define STM32_NDAC            0  /* One DAC channel */
 #  define STM32_NCOMP           0  /* Two Analog Comparators */
 #  define STM32_NCAP            0  /* Capacitive sensing channels (14 on UFQFPN32)) */
-#  define STM32_NPORTS          5  /* Six GPIO ports, GPIOA-F */
+#  define STM32_NPORTS          5  /* Five GPIO ports, GPIOA-D, F */
 
 #elif defined(CONFIG_ARCH_CHIP_STM32F051R8)
 
@@ -244,7 +244,7 @@
 #  define STM32_NCRC            1  /* No CRC module */
 #  define STM32_NRNG            0  /* No Random number generator (RNG) */
 #  define STM32_NCAP            0  /* No Capacitive sensing channels */
-#  define STM32_NPORTS          5  /* Five GPIO ports, GPIOA-D, F */
+#  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-F */
 
 #elif defined(CONFIG_ARCH_CHIP_STM32G071EB)   || defined(CONFIG_ARCH_CHIP_STM32G071G8)   || \
       defined(CONFIG_ARCH_CHIP_STM32G071GB)   || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \
@@ -277,7 +277,7 @@
 #  define STM32_NCRC            0  /* No CRC module */
 #  define STM32_NRNG            0  /* No Random number generator (RNG) */
 #  define STM32_NCAP            0  /* No Capacitive sensing channels */
-#  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-E, H */
+#  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-F */
 
 /* STM32L EnergyLite Line ***************************************************/
 
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
index 487b44d842..4a1700a397 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
@@ -112,6 +112,7 @@
 #define STM32_GPIOB_BASE     0x50000400     /* 0x50000400-0x500007ff: GPIO Port B */
 #define STM32_GPIOC_BASE     0x50000800     /* 0x50000800-0x50000bff: GPIO Port C */
 #define STM32_GPIOD_BASE     0X50000C00     /* 0x50000c00-0x50000fff: GPIO Port D */
+#define STM32_GPIOE_BASE     0X50001000     /* 0x50001000-0x500013ff: GPIO Port E */
 #define STM32_GPIOF_BASE     0x50001400     /* 0x50001400-0x500017ff: GPIO Port F */
 
 /* Cortex-M4 Base Addresses *************************************************/