drivers/mtd/st25fl1.c: Add a driver for ST25FL1*K QuadSPI FLASH parts
This commit is contained in:
Gregory Nutt
parent
e983e547e1
commit
94ecf7ebad
@ -10881,4 +10881,6 @@
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device (2015-08-24).
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* networking: Correct return value from psock_tcp_accept(). From
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SaeHie Park (2015-08-25).
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* drivers/mtd/st25fl1.c: Add a driver for ST25L1*K QuadSPI parts
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(2015-08-15).
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@ -92,6 +92,10 @@ ifeq ($(CONFIG_MTD_AT25),y)
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CSRCS += at25.c
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endif
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ifeq ($(CONFIG_MTD_ST25FL1),y)
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CSRCS += st25fl1.c
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endif
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ifeq ($(CONFIG_MTD_SMART),y)
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ifeq ($(CONFIG_FS_SMARTFS),y)
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CSRCS += smart.c
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935
drivers/mtd/st25fl1.c
Normal file
935
drivers/mtd/st25fl1.c
Normal file
@ -0,0 +1,935 @@
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/************************************************************************************
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* drivers/mtd/st25fl1.c
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* Driver for QuadSPI-based S25FL116K, S25FL132K, and S25L164K
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <string.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/fs/ioctl.h>
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#include <nuttx/spi/spi.h>
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#include <nuttx/mtd/mtd.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* QuadSPI Mode */
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#ifndef CONFIG_ST25FL1_SPIMODE
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# define CONFIG_ST25FL1_SPIMODE SPIDEV_MODE0
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#endif
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/* QuadSPI Frequency. May be up to 25MHz. */
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#ifndef CONFIG_ST25FL1_SPIFREQUENCY
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# define CONFIG_ST25FL1_SPIFREQUENCY 20000000
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#endif
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/* ST25FL1 Commands *****************************************************************/
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/* Configuration, Status, Erase, Program Commands ***********************************/
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/* Command Value Description: */
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/* Data sequence */
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#define ST25FL1_READ_STATUS1 0x05 /* Read status register 1: *
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* 0x05 | SR1 */
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#define ST25FL1_READ_STATUS2 0x35 /* Read status register 2: *
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* 0x35 | SR2 */
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#define ST25FL1_READ_STATUS3 0x33 /* Read status register 3: *
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* 0x33 | SR3 */
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#define ST25FL1_WRITE_ENABLE 0x06 /* Write enable: *
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* 0x06 */
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#define ST25FL1_VWRITE_ENABLE 0x50 /* Write enable for volatile status: *
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* 0x50 */
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#define ST25FL1_WRITE_DISABLE 0x04 /* Write disable command code: *
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* 0x04 */
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#define ST25FL1_WRITE_STATUS 0x01 /* Write status register: *
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* 0x01 | SR1 | SR2 | SR3 */
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#define ST25FL1_WRAP_ENABLE 0x77 /* Set Burst with Wrap: *
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* 0x77 | xx | xx | xx | SR3 */
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#define ST25FL1_UNPROTECT_SECTOR 0x39 /* Set Block / Pointer Protection: *
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* 0x39 | ADDR(MS) | ADDR(MID) | xx */
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#define ST25FL1_PAGE_PROGRAM 0x02 /* Page Program: *
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* 0x02 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | data */
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#define ST25FL1_SECTOR_ERASE 0x20 /* Sector Erase (4 kB) *
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* 0x02 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) */
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#define ST25FL1_BLOCK_ERASE 0xd8 /* Block Erase (64 kB): *
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* 0x02 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) */
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#define ST25FL1_CHIP_ERASE_1 0x60 /* Chip Erase 1: *
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* 0x60 */
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#define ST25FL1_CHIP_ERASE_2 0xc7 /* Chip Erase 2: *
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* 0xc7 */
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#define ST25FL1_ERASE_PROG_SUSPEND 0x75 /* Erase / Program Suspend: *
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* 0x75 */
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#define ST25FL1_ERASE_PROG_RESUME 0x7a /* Erase / Program Resume: *
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* 0x7a */
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/* Read Commands ********************************************************************/
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/* Command Value Description: */
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/* Data sequence */
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#define ST25FL1_READ_DATA 0x03 /* Read Data: *
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* 0x03 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | data... */
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#define ST25FL1_FAST_READ 0x0b /* Fast Read: *
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* 0x0b | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | dummy | data... */
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#define ST25FL1_FAST_READ_DUAL 0x3b /* Fast Read Dual Output: *
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* 0x3b | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | dummy | data... */
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#define ST25FL1_FAST_READ_QUAD 0x6b /* Fast Read Dual Output: *
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* 0x6b | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | dummy | data... */
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#define ST25FL1_FAST_READ_DUALIO 0xbb /* Fast Read Dual I/O: *
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* 0xbb | ADDR(MS) | ADDR(LS) | data... */
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#define ST25FL1_FAST_READ_QUADIO 0xeb /* Fast Read Quad I/O: *
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* 0xeb | ADDR | data... */
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#define ST25FL1_CONT_READ_RESET 0xff /* Continuous Read Mode Reset: *
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* 0xff | 0xff */
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/* Reset Commands *******************************************************************/
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/* Command Value Description: */
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/* Data sequence */
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#define ST25FL1_SOFT_RESET_ENABLE 0x66 /* Software Reset Enable: *
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* 0x66 */
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#define ST25FL1_SOFT_RESET 0x99 /* Software Reset: *
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* 0x99 */
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/* Continuous Read Mode Reset: *
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* 0xff | 0xff */
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/* ID/Security Commands *************************&***********************************/
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/* Command Value Description: */
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/* Data sequence */
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#define ST25FL1_DEEP_PWRDOWN 0xb9 /* Deep Power-down: *
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* 0xb9 */
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#define ST25FL1_RELEASE_PWRDOWN 0xab /* Release Power down / Device ID: *
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* 0xab | dummy | dummy | dummy | *
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* DeviceID */
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#define ST25FL1_MANUFACTURER 0x90 /* Manufacturer / Device ID: *
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* 0x90 | dummy | dummy | 0x00 | *
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* Manufacturer | DeviceID */
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#define ST25FL1_JEDEC_ID 0x9f /* JEDEC ID: *
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* 0x9f | Manufacturer | MemoryType | *
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* Capacity */
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#define ST25FL1_READ_SFDP 0x5a /* Read SFDP Register / Read Unique ID *
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* Number: *
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* 0x5a | 0x00 | 0x00 | ADDR | dummy | *
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* data... */
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#define ST25FL1_READ_SECURITY 0x48 /* Read Security Registers: *
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* 0x48 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | dummy | data... */
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#define ST25FL1_ERASE_SECURITY 0x44 /* Erase Security Registers: *
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* 0x48 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) */
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#define ST25FL1_PROgRAM_SECURITY 0x42 /* Program Security Registers: *
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* 0x42 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | data... */
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/* Flash Manufacturer JEDEC IDs */
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#define ST25FL1_JEDEC_ID_ATMEL 0x1f
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#define ST25FL1_JEDEC_ID_ST 0x20
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#define ST25FL1_JEDEC_ID_SST 0xbf
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#define ST25FL1_JEDEC_ID_MACRONIX 0xc2
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#define ST25FL1_JEDEC_ID_WINBOND 0xef
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/* ST25FL1 Registers ****************************************************************/
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/* Status register bit definitions */
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#define STATUS1_BUSY_MASK (1 << 0) /* Bit 0: Device ready/busy status */
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# define STATUS1_READY (0 << 0) /* 0 = Not Busy */
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# define STATUS1_BUSY (1 << 0) /* 1 = Busy */
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#define STATUS1_WEL_MASK (1 << 1) /* Bit 1: Write enable latch status */
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# define STATUS1_WEL_DISABLED (0 << 1) /* 0 = Not Write Enabled */
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# define STATUS1_WEL_ENABLED (1 << 1) /* 1 = Write Enabled */
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#define STATUS1_BP_SHIFT (2) /* Bits 2-4: Block protect bits */
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#define STATUS1_BP_MASK (7 << STATUS1_BP_SHIFT)
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# define STATUS1_BP_NONE (0 << STATUS1_BP_SHIFT)
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# define STATUS1_BP_ALL (7 << STATUS1_BP_SHIFT)
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#define STATUS1_TB_MASK (1 << 5) /* Bit 5: Top / Bottom Protect */
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# define STATUS1_TB_TOP (0 << 5) /* 0 = BP2-BP0 protect Top down */
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# define STATUS1_TB_BOTTOM (1 << 5) /* 1 = BP2-BP0 protect Bottom up */
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#define STATUS1_SEC_MASK (1 << 6) /* Bit 6: Sector / Block Protect */
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# define STATUS1_SEC_BLOCK (0 << 6) /* 0 = BP2-BP0 protect 64-kB blocks */
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# define STATUS1_SEC_BLOCK (1 << 6) /* 1 = BP2-BP0 protect 4-kB sectors */
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#define STATUS1_SRP0_MASK (1 << 7) /* Bit 7: Status register protect 0 */
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# define STATUS1_SRP0_UNLOCKED (0 << 7) /* 0 = WP# no effect / PS Lock Down */
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# define STATUS1_SRP0_LOCKED (1 << 7) /* 1 = WP# protect / OTP Lock Down */
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#define STATUS2_SRP1_MASK (1 << 0) /* Bit 0: Status register protect 1 */
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# define STATUS2_SRP1_UNLOCKED (0 << 0) /* 0 = WP# no effect / PS Lock Down */
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# define STATUS2_SRP1_LOCKED (1 << 0) /* 1 = WP# protect / OTP Lock Down */
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#define STATUS2_QUAD_ENABLE_MASK (1 << 1) /* Bit 1: Quad Enable */
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# define STATUS2_QUAD_DISABLE (0 << 1) /* 0 = Quad Mode Not Enabled */
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# define STATUS2_QUAD_ENABLE (1 << 1) /* 1 = Quad Mode Enabled */
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#define STATUS2_LB_SHIFT (2) /* Bits 2-5: Security Register Lock */
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#define STATUS2_LB_MASK (15 << STATUS2_LB_SHIFT)
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# define STATUS2_LB_NONE (0 << STATUS2_LB_SHIFT)
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# define STATUS2_LB_ALL (15 << STATUS2_LB_SHIFT)
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#define STATUS2_CMP_MASK (1 << 6) /* Bit 6: Complement Protect */
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# define STATUS2_CMP_NORMAL (0 << 6) /* 0 = Normal Protection Map */
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# define STATUS2_CMP_INVERTED (1 << 6) /* 1 = Inverted Protection Map */
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#define STATUS2_SUS_MASK (1 << 7) /* Bit 7: Suspend Status */
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# define STATUS2_SUS_NONE (0 << 7) /* 0 = Erase / Program not suspended */
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# define STATUS2_SUS_SUSPENDED (1 << 7) /* 1 = Erase / Program suspended */
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#define STATUS3_LC_SHIFT (0) /* Bits 0-3: Latency control */
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#define STATUS3_LC_MASK (15 << STATUS3_LC_SHIFT)
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#define STATUS3_W4_MASK (1 << 4) /* Bit 4: Burst Wrap Enable */
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# define STATUS3_W4_DISABLED (0 << 4) /* 0 = Wrap Enabled */
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# define STATUS3_W4_ENABLED (1 << 4) /* 1 = Wrap Disabled */
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#define STATUS3_W56_SHIFT (5) /* Bits 5-6: Burst Wrap Length */
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#define STATUS3_W56_MASK (3 << STATUS3_W56_SHIFT)
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# define STATUS3_W56_8BYTE (0 << STATUS3_W56_SHIFT)
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# define STATUS3_W56_16BYTE (1 << STATUS3_W56_SHIFT)
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# define STATUS3_W56_32BYTE (2 << STATUS3_W56_SHIFT)
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# define STATUS3_W56_63BYTE (3 << STATUS3_W56_SHIFT)
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/* Bit 7: Reserved */
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/* Chip Geometries ******************************************************************/
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/* All members of the family support uniform 4K-byte sectors */
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#define S25FL116K_SECTOR_SIZE (4*1024)
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#define S25FL116K_SECTOR_COUNT (512)
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#define S25FL132K_SECTOR_SIZE (4*1024)
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#define S25FL132K_SECTOR_COUNT (1024)
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#define S25FL164K_SECTOR_SIZE (4*1024)
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#define S25FL164K_SECTOR_COUNT (2048)
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/* Cache flags **********************************************************************/
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#define ST25FL1_CACHE_VALID (1 << 0) /* 1=Cache has valid data */
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#define ST25FL1_CACHE_DIRTY (1 << 1) /* 1=Cache is dirty */
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#define ST25FL1_CACHE_ERASED (1 << 2) /* 1=Backing FLASH is erased */
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#define IS_VALID(p) ((((p)->flags) & ST25FL1_CACHE_VALID) != 0)
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#define IS_DIRTY(p) ((((p)->flags) & ST25FL1_CACHE_DIRTY) != 0)
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#define IS_ERASED(p) ((((p)->flags) & ST25FL1_CACHE_DIRTY) != 0)
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#define SET_VALID(p) do { (p)->flags |= ST25FL1_CACHE_VALID; } while (0)
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#define SET_DIRTY(p) do { (p)->flags |= ST25FL1_CACHE_DIRTY; } while (0)
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#define SET_ERASED(p) do { (p)->flags |= ST25FL1_CACHE_DIRTY; } while (0)
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#define CLR_VALID(p) do { (p)->flags &= ~ST25FL1_CACHE_VALID; } while (0)
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#define CLR_DIRTY(p) do { (p)->flags &= ~ST25FL1_CACHE_DIRTY; } while (0)
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#define CLR_ERASED(p) do { (p)->flags &= ~ST25FL1_CACHE_DIRTY; } while (0)
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/************************************************************************************
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* Private Types
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************************************************************************************/
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/* This type represents the state of the MTD device. The struct mtd_dev_s must
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* appear at the beginning of the definition so that you can freely cast between
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* pointers to struct mtd_dev_s and struct st25fl1_dev_s.
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*/
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struct st25fl1_dev_s
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{
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struct mtd_dev_s mtd; /* MTD interface */
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FAR struct spi_dev_s *spi; /* Saved QuadSPI interface instance */
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uint16_t nsectors; /* Number of erase sectors */
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#ifdef CONFIG_ST25FL1_SECTOR512
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uint8_t flags; /* Buffered sector flags */
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uint16_t esectno; /* Erase sector number in the cache*/
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FAR uint8_t *sector; /* Allocated sector data */
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#endif
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};
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/************************************************************************************
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* Private Function Prototypes
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************************************************************************************/
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/* Helpers */
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static void st25fl1_lock(FAR struct spi_dev_s *spi);
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static inline void st25fl1_unlock(FAR struct spi_dev_s *spi);
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static inline int st25fl1_readid(FAR struct st25fl1_dev_s *priv);
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static void st25fl1_unprotect(FAR struct st25fl1_dev_s *priv);
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static uint8_t st25fl1_waitwritecomplete(FAR struct st25fl1_dev_s *priv);
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static inline void st25fl1_wren(FAR struct st25fl1_dev_s *priv);
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static inline void st25fl1_wrdi(FAR struct st25fl1_dev_s *priv);
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static void st25fl1_sectorerase(FAR struct st25fl1_dev_s *priv, off_t offset);
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static inline int st25fl1_chiperase(FAR struct st25fl1_dev_s *priv);
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static void st25fl1_byteread(FAR struct st25fl1_dev_s *priv, FAR uint8_t *buffer,
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off_t address, size_t nbytes);
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static void st25fl1_pagewrite(FAR struct st25fl1_dev_s *priv, FAR const uint8_t *buffer,
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off_t address, size_t nbytes);
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#ifdef CONFIG_ST25FL1_SECTOR512
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static void st25fl1_cacheflush(struct st25fl1_dev_s *priv);
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static FAR uint8_t *st25fl1_cacheread(struct st25fl1_dev_s *priv, off_t sector);
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static void st25fl1_cacheerase(struct st25fl1_dev_s *priv, off_t sector);
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static void st25fl1_cachewrite(FAR struct st25fl1_dev_s *priv, FAR const uint8_t *buffer,
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off_t sector, size_t nsectors);
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#endif
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/* MTD driver methods */
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static int st25fl1_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks);
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static ssize_t st25fl1_bread(FAR struct mtd_dev_s *dev, off_t startblock,
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size_t nblocks, FAR uint8_t *buf);
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static ssize_t st25fl1_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
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size_t nblocks, FAR const uint8_t *buf);
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static ssize_t st25fl1_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
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FAR uint8_t *buffer);
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static int st25fl1_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg);
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/************************************************************************************
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* Private Data
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************************************************************************************/
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Name: st25fl1_lock
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************************************************************************************/
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static void st25fl1_lock(FAR struct spi_dev_s *spi)
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{
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/* On QuadSPI busses where there are multiple devices, it will be necessary to
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* lock QuadSPI to have exclusive access to the busses for a sequence of
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* transfers. The bus should be locked before the chip is selected.
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*
|
||||
* This is a blocking call and will not return until we have exclusiv access to
|
||||
* the QuadSPI buss. We will retain that exclusive access until the bus is unlocked.
|
||||
*/
|
||||
|
||||
(void)SPI_LOCK(spi, true);
|
||||
|
||||
/* After locking the QuadSPI bus, the we also need call the setfrequency, setbits, and
|
||||
* setmode methods to make sure that the QuadSPI is properly configured for the device.
|
||||
* If the QuadSPI buss is being shared, then it may have been left in an incompatible
|
||||
* state.
|
||||
*/
|
||||
|
||||
SPI_SETMODE(spi, CONFIG_ST25FL1_SPIMODE);
|
||||
SPI_SETBITS(spi, 8);
|
||||
(void)SPI_SETFREQUENCY(spi, CONFIG_ST25FL1_SPIFREQUENCY);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_unlock
|
||||
************************************************************************************/
|
||||
|
||||
static inline void st25fl1_unlock(FAR struct spi_dev_s *spi)
|
||||
{
|
||||
(void)SPI_LOCK(spi, false);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_readid
|
||||
************************************************************************************/
|
||||
|
||||
static inline int st25fl1_readid(struct st25fl1_dev_s *priv)
|
||||
{
|
||||
uint16_t manufacturer;
|
||||
uint16_t memory;
|
||||
uint16_t capacity;
|
||||
|
||||
fvdbg("priv: %p\n", priv);
|
||||
|
||||
/* Lock the QuadSPI bus, configure the bus, and select this FLASH part. */
|
||||
|
||||
st25fl1_lock(priv->spi);
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||||
|
||||
#warning Missing Logic
|
||||
|
||||
/* Deselect the FLASH and unlock the bus */
|
||||
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||||
st25fl1_unlock(priv->spi);
|
||||
|
||||
fvdbg("manufacturer: %02x memory: %02x capacity: %02x\n",
|
||||
manufacturer, memory, capacity);
|
||||
|
||||
/* Check for a valid manufacturer and memory type */
|
||||
#warning Missing Logic
|
||||
|
||||
/* We don't understand the manufacturer or the memory type */
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_unprotect
|
||||
************************************************************************************/
|
||||
|
||||
static void st25fl1_unprotect(FAR struct st25fl1_dev_s *priv)
|
||||
{
|
||||
#warning Missing Logic
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_waitwritecomplete
|
||||
************************************************************************************/
|
||||
|
||||
static uint8_t st25fl1_waitwritecomplete(struct st25fl1_dev_s *priv)
|
||||
{
|
||||
uint8_t status;
|
||||
|
||||
/* Are we the only device on the bus? */
|
||||
|
||||
#ifdef CONFIG_SPI_OWNBUS
|
||||
|
||||
/* Select this FLASH part */
|
||||
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||||
#warning Missing Logic
|
||||
|
||||
/* Deselect the FLASH */
|
||||
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||||
|
||||
#else
|
||||
|
||||
/* Loop as long as the memory is busy with a write cycle */
|
||||
|
||||
do
|
||||
{
|
||||
/* Select this FLASH part */
|
||||
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||||
#warning Missing Logic
|
||||
/* Deselect the FLASH */
|
||||
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||||
}
|
||||
while ((status & ST25FL1_SR_BUSY) != 0);
|
||||
#endif
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_wren
|
||||
************************************************************************************/
|
||||
|
||||
static inline void st25fl1_wren(struct st25fl1_dev_s *priv)
|
||||
{
|
||||
/* Select this FLASH part */
|
||||
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||||
#warning Missing Logic
|
||||
/* Deselect the FLASH */
|
||||
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_wrdi
|
||||
************************************************************************************/
|
||||
|
||||
static inline void st25fl1_wrdi(struct st25fl1_dev_s *priv)
|
||||
{
|
||||
/* Select this FLASH part */
|
||||
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||||
#warning Missing Logic
|
||||
/* Deselect the FLASH */
|
||||
|
||||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_sectorerase
|
||||
************************************************************************************/
|
||||
|
||||
static void st25fl1_sectorerase(struct st25fl1_dev_s *priv, off_t sector)
|
||||
{
|
||||
fvdbg("sector: %08lx\n", (long)sector);
|
||||
#warning Missing Logic
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_chiperase
|
||||
************************************************************************************/
|
||||
|
||||
static inline int st25fl1_chiperase(struct st25fl1_dev_s *priv)
|
||||
{
|
||||
fvdbg("priv: %p\n", priv);
|
||||
#warning Missing Logic
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_byteread
|
||||
************************************************************************************/
|
||||
|
||||
static void st25fl1_byteread(FAR struct st25fl1_dev_s *priv, FAR uint8_t *buffer,
|
||||
off_t address, size_t nbytes)
|
||||
{
|
||||
fvdbg("address: %08lx nbytes: %d\n", (long)address, (int)nbytes);
|
||||
#warning Missing Logic
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_pagewrite
|
||||
************************************************************************************/
|
||||
|
||||
static void st25fl1_pagewrite(struct st25fl1_dev_s *priv, FAR const uint8_t *buffer,
|
||||
off_t address, size_t nbytes)
|
||||
{
|
||||
fvdbg("address: %08lx nwords: %d\n", (long)address, (int)nbytes);
|
||||
#warning Missing Logic
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_cacheflush
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ST25FL1_SECTOR512
|
||||
static void st25fl1_cacheflush(struct st25fl1_dev_s *priv)
|
||||
{
|
||||
/* If the cached is dirty (meaning that it no longer matches the old FLASH contents)
|
||||
* or was erased (with the cache containing the correct FLASH contents), then write
|
||||
* the cached erase block to FLASH.
|
||||
*/
|
||||
|
||||
if (IS_DIRTY(priv) || IS_ERASED(priv))
|
||||
{
|
||||
/* Write entire erase block to FLASH */
|
||||
#warning Missing Logic
|
||||
|
||||
/* The case is no long dirty and the FLASH is no longer erased */
|
||||
|
||||
CLR_DIRTY(priv);
|
||||
CLR_ERASED(priv);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_cacheread
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ST25FL1_SECTOR512
|
||||
static FAR uint8_t *st25fl1_cacheread(struct st25fl1_dev_s *priv, off_t sector)
|
||||
{
|
||||
off_t esectno;
|
||||
int shift;
|
||||
int index;
|
||||
|
||||
/* Convert from the 512 byte sector to the erase sector size of the device. For
|
||||
* exmample, if the actual erase sector size if 4Kb (1 << 12), then we first
|
||||
* shift to the right by 3 to get the sector number in 4096 increments.
|
||||
*/
|
||||
|
||||
shift = ST25FL1_SECTOR_SHIFT - ST25FL1_SECTOR512_SHIFT;
|
||||
esectno = sector >> shift;
|
||||
fvdbg("sector: %ld esectno: %d shift=%d\n", sector, esectno, shift);
|
||||
|
||||
/* Check if the requested erase block is already in the cache */
|
||||
|
||||
if (!IS_VALID(priv) || esectno != priv->esectno)
|
||||
{
|
||||
/* No.. Flush any dirty erase block currently in the cache */
|
||||
|
||||
st25fl1_cacheflush(priv);
|
||||
|
||||
/* Read the erase block into the cache */
|
||||
|
||||
st25fl1_byteread(priv, priv->sector, (esectno << ST25FL1_SECTOR_SHIFT), ST25FL1_SECTOR_SIZE);
|
||||
|
||||
/* Mark the sector as cached */
|
||||
|
||||
priv->esectno = esectno;
|
||||
|
||||
SET_VALID(priv); /* The data in the cache is valid */
|
||||
CLR_DIRTY(priv); /* It should match the FLASH contents */
|
||||
CLR_ERASED(priv); /* The underlying FLASH has not been erased */
|
||||
}
|
||||
|
||||
/* Get the index to the 512 sector in the erase block that holds the argument */
|
||||
|
||||
index = sector & ((1 << shift) - 1);
|
||||
|
||||
/* Return the address in the cache that holds this sector */
|
||||
|
||||
return &priv->sector[index << ST25FL1_SECTOR512_SHIFT];
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_cacheerase
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ST25FL1_SECTOR512
|
||||
static void st25fl1_cacheerase(struct st25fl1_dev_s *priv, off_t sector)
|
||||
{
|
||||
FAR uint8_t *dest;
|
||||
|
||||
/* First, make sure that the erase block containing the 512 byte sector is in
|
||||
* the cache.
|
||||
*/
|
||||
|
||||
dest = st25fl1_cacheread(priv, sector);
|
||||
|
||||
/* Erase the block containing this sector if it is not already erased.
|
||||
* The erased indicated will be cleared when the data from the erase sector
|
||||
* is read into the cache and set here when we erase the block.
|
||||
*/
|
||||
|
||||
if (!IS_ERASED(priv))
|
||||
{
|
||||
off_t esectno = sector >> (ST25FL1_SECTOR_SHIFT - ST25FL1_SECTOR512_SHIFT);
|
||||
fvdbg("sector: %ld esectno: %d\n", sector, esectno);
|
||||
|
||||
st25fl1_sectorerase(priv, esectno);
|
||||
SET_ERASED(priv);
|
||||
}
|
||||
|
||||
/* Put the cached sector data into the erase state and mart the cache as dirty
|
||||
* (but don't update the FLASH yet. The caller will do that at a more optimal
|
||||
* time).
|
||||
*/
|
||||
|
||||
memset(dest, ST25FL1_ERASED_STATE, ST25FL1_SECTOR512_SIZE);
|
||||
SET_DIRTY(priv);
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_cachewrite
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ST25FL1_SECTOR512
|
||||
static void st25fl1_cachewrite(FAR struct st25fl1_dev_s *priv, FAR const uint8_t *buffer,
|
||||
off_t sector, size_t nsectors)
|
||||
{
|
||||
FAR uint8_t *dest;
|
||||
|
||||
for (; nsectors > 0; nsectors--)
|
||||
{
|
||||
/* First, make sure that the erase block containing 512 byte sector is in
|
||||
* memory.
|
||||
*/
|
||||
|
||||
dest = st25fl1_cacheread(priv, sector);
|
||||
|
||||
/* Erase the block containing this sector if it is not already erased.
|
||||
* The erased indicated will be cleared when the data from the erase sector
|
||||
* is read into the cache and set here when we erase the sector.
|
||||
*/
|
||||
|
||||
if (!IS_ERASED(priv))
|
||||
{
|
||||
off_t esectno = sector >> (ST25FL1_SECTOR_SHIFT - ST25FL1_SECTOR512_SHIFT);
|
||||
fvdbg("sector: %ld esectno: %d\n", sector, esectno);
|
||||
|
||||
st25fl1_sectorerase(priv, esectno);
|
||||
SET_ERASED(priv);
|
||||
}
|
||||
|
||||
/* Copy the new sector data into cached erase block */
|
||||
|
||||
memcpy(dest, buffer, ST25FL1_SECTOR512_SIZE);
|
||||
SET_DIRTY(priv);
|
||||
|
||||
/* Set up for the next 512 byte sector */
|
||||
|
||||
buffer += ST25FL1_SECTOR512_SIZE;
|
||||
sector++;
|
||||
}
|
||||
|
||||
/* Flush the last erase block left in the cache */
|
||||
|
||||
st25fl1_cacheflush(priv);
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_erase
|
||||
************************************************************************************/
|
||||
|
||||
static int st25fl1_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks)
|
||||
{
|
||||
FAR struct st25fl1_dev_s *priv = (FAR struct st25fl1_dev_s *)dev;
|
||||
|
||||
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
||||
#warning Missing Logic
|
||||
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_bread
|
||||
************************************************************************************/
|
||||
|
||||
static ssize_t st25fl1_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
|
||||
FAR uint8_t *buffer)
|
||||
{
|
||||
ssize_t nbytes;
|
||||
|
||||
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
||||
|
||||
/* On this device, we can handle the block read just like the byte-oriented read */
|
||||
|
||||
#ifdef CONFIG_ST25FL1_SECTOR512
|
||||
nbytes = st25fl1_read(dev, startblock << ST25FL1_SECTOR512_SHIFT, nblocks << ST25FL1_SECTOR512_SHIFT, buffer);
|
||||
if (nbytes > 0)
|
||||
{
|
||||
nbytes >>= ST25FL1_SECTOR512_SHIFT;
|
||||
}
|
||||
#else
|
||||
nbytes = st25fl1_read(dev, startblock << ST25FL1_SECTOR_SHIFT, nblocks << ST25FL1_SECTOR_SHIFT, buffer);
|
||||
if (nbytes > 0)
|
||||
{
|
||||
nbytes >>= ST25FL1_SECTOR_SHIFT;
|
||||
}
|
||||
#endif
|
||||
|
||||
return nbytes;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_bwrite
|
||||
************************************************************************************/
|
||||
|
||||
static ssize_t st25fl1_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
|
||||
FAR const uint8_t *buffer)
|
||||
{
|
||||
FAR struct st25fl1_dev_s *priv = (FAR struct st25fl1_dev_s *)dev;
|
||||
|
||||
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
||||
|
||||
/* Lock the QuadSPI bus and write all of the pages to FLASH */
|
||||
|
||||
st25fl1_lock(priv->spi);
|
||||
|
||||
#if defined(CONFIG_ST25FL1_SECTOR512)
|
||||
st25fl1_cachewrite(priv, buffer, startblock, nblocks);
|
||||
#else
|
||||
st25fl1_pagewrite(priv, buffer, startblock << ST25FL1_SECTOR_SHIFT,
|
||||
nblocks << ST25FL1_SECTOR_SHIFT);
|
||||
#endif
|
||||
st25fl1_unlock(priv->spi);
|
||||
|
||||
return nblocks;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_read
|
||||
************************************************************************************/
|
||||
|
||||
static ssize_t st25fl1_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
|
||||
FAR uint8_t *buffer)
|
||||
{
|
||||
FAR struct st25fl1_dev_s *priv = (FAR struct st25fl1_dev_s *)dev;
|
||||
|
||||
fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
|
||||
|
||||
/* Lock the QuadSPI bus and select this FLASH part */
|
||||
|
||||
st25fl1_lock(priv->spi);
|
||||
st25fl1_byteread(priv, buffer, offset, nbytes);
|
||||
st25fl1_unlock(priv->spi);
|
||||
|
||||
fvdbg("return nbytes: %d\n", (int)nbytes);
|
||||
return nbytes;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_ioctl
|
||||
************************************************************************************/
|
||||
|
||||
static int st25fl1_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
|
||||
{
|
||||
FAR struct st25fl1_dev_s *priv = (FAR struct st25fl1_dev_s *)dev;
|
||||
int ret = -EINVAL; /* Assume good command with bad parameters */
|
||||
|
||||
fvdbg("cmd: %d \n", cmd);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case MTDIOC_GEOMETRY:
|
||||
{
|
||||
FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)((uintptr_t)arg);
|
||||
if (geo)
|
||||
{
|
||||
/* Populate the geometry structure with information need to know
|
||||
* the capacity and how to access the device.
|
||||
*
|
||||
* NOTE: that the device is treated as though it where just an array
|
||||
* of fixed size blocks. That is most likely not true, but the client
|
||||
* will expect the device logic to do whatever is necessary to make it
|
||||
* appear so.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ST25FL1_SECTOR512
|
||||
geo->blocksize = (1 << ST25FL1_SECTOR512_SHIFT);
|
||||
geo->erasesize = (1 << ST25FL1_SECTOR512_SHIFT);
|
||||
geo->neraseblocks = priv->nsectors << (ST25FL1_SECTOR_SHIFT - ST25FL1_SECTOR512_SHIFT);
|
||||
#else
|
||||
geo->blocksize = ST25FL1_SECTOR_SIZE;
|
||||
geo->erasesize = ST25FL1_SECTOR_SIZE;
|
||||
geo->neraseblocks = priv->nsectors;
|
||||
#endif
|
||||
ret = OK;
|
||||
|
||||
fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
|
||||
geo->blocksize, geo->erasesize, geo->neraseblocks);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case MTDIOC_BULKERASE:
|
||||
{
|
||||
/* Erase the entire device */
|
||||
|
||||
st25fl1_lock(priv->spi);
|
||||
ret = st25fl1_chiperase(priv);
|
||||
st25fl1_unlock(priv->spi);
|
||||
}
|
||||
break;
|
||||
|
||||
case MTDIOC_XIPBASE:
|
||||
default:
|
||||
ret = -ENOTTY; /* Bad command */
|
||||
break;
|
||||
}
|
||||
|
||||
fvdbg("return %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: st25fl1_initialize
|
||||
*
|
||||
* Description:
|
||||
* Create an initialize MTD device instance. MTD devices are not registered
|
||||
* in the file system, but are created as instances that can be bound to
|
||||
* other functions (such as a block or character driver front end).
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
FAR struct mtd_dev_s *st25fl1_initialize(FAR struct spi_dev_s *spi)
|
||||
{
|
||||
FAR struct st25fl1_dev_s *priv;
|
||||
int ret;
|
||||
|
||||
fvdbg("spi: %p\n", spi);
|
||||
|
||||
/* Allocate a state structure (we allocate the structure instead of using
|
||||
* a fixed, static allocation so that we can handle multiple FLASH devices.
|
||||
* The current implementation would handle only one FLASH part per QuadSPI
|
||||
* device (only because of the SPIDEV_FLASH definition) and so would have
|
||||
* to be extended to handle multiple FLASH parts on the same QuadSPI bus.
|
||||
*/
|
||||
|
||||
priv = (FAR struct st25fl1_dev_s *)kmm_zalloc(sizeof(struct st25fl1_dev_s));
|
||||
if (priv)
|
||||
{
|
||||
/* Initialize the allocated structure (unsupported methods were
|
||||
* nullified by kmm_zalloc).
|
||||
*/
|
||||
|
||||
priv->mtd.erase = st25fl1_erase;
|
||||
priv->mtd.bread = st25fl1_bread;
|
||||
priv->mtd.bwrite = st25fl1_bwrite;
|
||||
priv->mtd.read = st25fl1_read;
|
||||
priv->mtd.ioctl = st25fl1_ioctl;
|
||||
priv->spi = spi;
|
||||
|
||||
/* Deselect the FLASH */
|
||||
|
||||
SPI_SELECT(spi, SPIDEV_FLASH, false);
|
||||
|
||||
/* Identify the FLASH chip and get its capacity */
|
||||
|
||||
ret = st25fl1_readid(priv);
|
||||
if (ret != OK)
|
||||
{
|
||||
/* Unrecognized! Discard all of that work we just did and return NULL */
|
||||
|
||||
fdbg("Unrecognized\n");
|
||||
kmm_free(priv);
|
||||
priv = NULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Make sure that the FLASH is unprotected so that we can write into it */
|
||||
|
||||
st25fl1_unprotect(priv);
|
||||
|
||||
#ifdef CONFIG_ST25FL1_SECTOR512 /* Simulate a 512 byte sector */
|
||||
/* Allocate a buffer for the erase block cache */
|
||||
|
||||
priv->sector = (FAR uint8_t *)kmm_malloc(ST25FL1_SECTOR_SIZE);
|
||||
if (!priv->sector)
|
||||
{
|
||||
/* Allocation failed! Discard all of that work we just did and return NULL */
|
||||
|
||||
fdbg("Allocation failed\n");
|
||||
kmm_free(priv);
|
||||
priv = NULL;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/* Register the MTD with the procfs system if enabled */
|
||||
|
||||
#ifdef CONFIG_MTD_REGISTRATION
|
||||
mtd_register(&priv->mtd, "st25fl1");
|
||||
#endif
|
||||
|
||||
/* Return the implementation-specific state structure as the MTD device */
|
||||
|
||||
fvdbg("Return %p\n", priv);
|
||||
return (FAR struct mtd_dev_s *)priv;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user