From 94fca00261586b207302673e8a09b366e60e4245 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 17 Oct 2009 20:42:37 +0000 Subject: [PATCH] Fix major bug in STM32 interrupt enable/disable logic; NSH now works on STM32 git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2149 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/src/lm3s/lm3s_irq.c | 12 ++++++------ arch/arm/src/stm32/stm32_irq.c | 26 ++++++++++++++++---------- arch/arm/src/stm32/stm32_lowputc.c | 2 +- arch/arm/src/stm32/stm32_serial.c | 14 +++++++------- 4 files changed, 30 insertions(+), 24 deletions(-) diff --git a/arch/arm/src/lm3s/lm3s_irq.c b/arch/arm/src/lm3s/lm3s_irq.c index d4101b1ae6..63744581a2 100644 --- a/arch/arm/src/lm3s/lm3s_irq.c +++ b/arch/arm/src/lm3s/lm3s_irq.c @@ -61,7 +61,7 @@ * bringup */ -#undef LM2S_IRQ_DEBUG +#undef LM3S_IRQ_DEBUG /* Get a 32-bit version of the default priority */ @@ -93,7 +93,7 @@ uint32 *current_regs; * ****************************************************************************/ -#if defined(LM2S_IRQ_DEBUG) && defined (CONFIG_DEBUG) +#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG) static void lm3s_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -197,7 +197,7 @@ static int lm3s_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: lml3s_irqinfo + * Name: lm3s_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -205,7 +205,7 @@ static int lm3s_reserved(int irq, FAR void *context) * ****************************************************************************/ -static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit) +static int lm3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit) { DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS); @@ -367,7 +367,7 @@ void up_disable_irq(int irq) uint32 regval; uint32 bit; - if (lml3s_irqinfo(irq, ®addr, &bit) == 0) + if (lm3s_irqinfo(irq, ®addr, &bit) == 0) { /* Clear the appropriate bit in the register to enable the interrupt */ @@ -392,7 +392,7 @@ void up_enable_irq(int irq) uint32 regval; uint32 bit; - if (lml3s_irqinfo(irq, ®addr, &bit) == 0) + if (lm3s_irqinfo(irq, ®addr, &bit) == 0) { /* Set the appropriate bit in the register to enable the interrupt */ diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index cc5a16dda3..a7bb4c9e82 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -61,7 +61,7 @@ * bringup */ -#undef LM2S_IRQ_DEBUG +#undef STM32_IRQ_DEBUG /* Get a 32-bit version of the default priority */ @@ -93,7 +93,7 @@ uint32 *current_regs; * ****************************************************************************/ -#if defined(LM2S_IRQ_DEBUG) && defined (CONFIG_DEBUG) +#if defined(STM32_IRQ_DEBUG) && defined (CONFIG_DEBUG) static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -107,8 +107,9 @@ static void stm32_dumpnvic(const char *msg, int irq) getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); #endif - slldbg(" IRQ ENABLE: %08x %08x\n", - getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE)); + slldbg(" IRQ ENABLE: %08x %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE), + getreg32(NVIC_IRQ64_95_ENABLE)); slldbg(" SYSH_PRIO: %08x %08x %08x\n", getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), getreg32(NVIC_SYSH12_15_PRIORITY)); @@ -121,6 +122,11 @@ static void stm32_dumpnvic(const char *msg, int irq) slldbg(" %08x %08x %08x %08x\n", getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + slldbg(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY)); + slldbg(" %08x\n", + getreg32(NVIC_IRQ64_67_PRIORITY)); irqrestore(flags); } #else @@ -197,7 +203,7 @@ static int stm32_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: lml3s_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -205,7 +211,7 @@ static int stm32_reserved(int irq, FAR void *context) * ****************************************************************************/ -static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit) +static int stm32_irqinfo(int irq, uint32 *regaddr, uint32 *bit) { DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); @@ -220,8 +226,8 @@ static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit) } if (irq < STM32_IRQ_INTERRUPTS + 64) { - *regaddr = NVIC_IRQ0_31_ENABLE; - *bit = 1 << (irq - STM32_IRQ_INTERRUPTS); + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (irq - STM32_IRQ_INTERRUPTS - 32); } else if (irq < NR_IRQS) { @@ -376,7 +382,7 @@ void up_disable_irq(int irq) uint32 regval; uint32 bit; - if (lml3s_irqinfo(irq, ®addr, &bit) == 0) + if (stm32_irqinfo(irq, ®addr, &bit) == 0) { /* Clear the appropriate bit in the register to enable the interrupt */ @@ -401,7 +407,7 @@ void up_enable_irq(int irq) uint32 regval; uint32 bit; - if (lml3s_irqinfo(irq, ®addr, &bit) == 0) + if (stm32_irqinfo(irq, ®addr, &bit) == 0) { /* Set the appropriate bit in the register to enable the interrupt */ diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/stm32/stm32_lowputc.c index 692ef679a2..05e9d412e2 100644 --- a/arch/arm/src/stm32/stm32_lowputc.c +++ b/arch/arm/src/stm32/stm32_lowputc.c @@ -218,7 +218,7 @@ void up_lowputc(char ch) { #ifdef HAVE_CONSOLE - /* Wait until the TX FIFO is not full */ + /* Wait until the TX data register is empty */ while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) == 0); diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 3bdaa31c74..5d946c7c81 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -413,8 +413,8 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16 *ie) * Name: up_setup * * Description: - * Configure the USART baud, bits, parity, fifos, etc. This method is - * called the first time that the serial port is opened. + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. * ****************************************************************************/ @@ -824,8 +824,8 @@ static void up_rxint(struct uart_dev_s *dev, boolean enable) ie = priv->ie; if (enable) { - /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx - * timeout occurs. + /* Receive an interrupt when their is anything in the Rx data register (or an Rx + * timeout occurs). */ #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -850,7 +850,7 @@ static void up_rxint(struct uart_dev_s *dev, boolean enable) * Name: up_rxavailable * * Description: - * Return TRUE if the receive fifo is not empty + * Return TRUE if the receive register is not empty * ****************************************************************************/ @@ -899,7 +899,7 @@ static void up_txint(struct uart_dev_s *dev, boolean enable) flags = irqsave(); if (enable) { - /* Set to receive an interrupt when the TX fifo is half emptied */ + /* Set to receive an interrupt when the TX data register is empty */ #ifndef CONFIG_SUPPRESS_SERIAL_INTS up_restoreusartint(priv, priv->ie | USART_CR1_TXEIE); @@ -924,7 +924,7 @@ static void up_txint(struct uart_dev_s *dev, boolean enable) * Name: up_txready * * Description: - * Return TRUE if the tranmsit fifo is not full + * Return TRUE if the tranmsit data register is empty * ****************************************************************************/