Tiva Timer: Add more interrupt management logic
This commit is contained in:
Gregory Nutt
parent
59555646c5
commit
9531dd1a80
@ -665,124 +665,53 @@
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# define TIMER_SYNC_SYNCWT5_TATB TIMER_SYNC_SYNCWT5(TIMER_SYNC_TATB)
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#endif
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/* GPTM Interrupt Mask (IMR) */
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/* Common bit definitions used with:
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*
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* - GPTM Interrupt Mask (IMR)
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* - GPTM Raw Interrupt Status (RIS)
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* - GPTM Masked Interrupt Status (MIS)
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* - GPTM Interrupt Clear (ICR)
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*/
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#define TIMER_IMR_TATOIM (1 << 0) /* Bit 0: Timer A Time-Out Interrupt Mask */
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#define TIMER_INT_TATO (1 << 0) /* Bit 0: Timer A Time-Out Interrupt */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_IMR_CAMIM (1 << 1) /* Bit 1: GPTM Timer A Capture Mode Match Interrupt Mask */
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# define TIMER_IMR_CAEIM (1 << 2) /* Bit 2: GPTM Timer A Capture Mode Event Interrupt Mask */
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# define TIMER_IMR_RTCIM (1 << 3) /* Bit 3: GPTM RTC Interrupt Mask */
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# define TIMER_IMR_TAMIM (1 << 4) /* Bit 4: GPTM Timer A Match Interrupt Mask */
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# define TIMER_INT_CAM (1 << 1) /* Bit 1: GPTM Timer A Capture Mode Match Interrupt */
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# define TIMER_INT_CAE (1 << 2) /* Bit 2: GPTM Timer A Capture Mode Event Interrupt */
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# define TIMER_INT_RTC (1 << 3) /* Bit 3: GPTM RTC Interrupt */
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# define TIMER_INT_TAM (1 << 4) /* Bit 4: GPTM Timer A Match Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIMER_IMR_DMAAIM (1 << 5) /* Bit 5: GPTM Timer A DMA Done Interrupt Mask */
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# define TIMER_INT_DMAA (1 << 5) /* Bit 5: GPTM Timer A DMA Done Interrupt */
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#endif
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#define TIMER_INT_TBTO (1 << 8) /* Bit 8: GPTM Timer B Time-Out Interrupt */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_IMR_TBTOIM (1 << 8) /* Bit 8: GPTM Timer B Time-Out Interrupt Mask */
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# define TIMER_IMR_CBMIM (1 << 9) /* Bit 9: GPTM Timer B Capture Mode Match Interrupt Mask */
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# define TIMER_IMR_CBEIM (1 << 10) /* Bit 10: GPTM Timer B Capture Mode Event Interrupt Mask */
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# define TIMER_IMR_TBMIM (1 << 11) /* Bit 11: GPTM Timer B Match Interrupt Mask */
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# define TIMER_INT_CBM (1 << 9) /* Bit 9: GPTM Timer B Capture Mode Match Interrupt */
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# define TIMER_INT_CBE (1 << 10) /* Bit 10: GPTM Timer B Capture Mode Event Interrupt */
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# define TIMER_INT_TBM (1 << 11) /* Bit 11: GPTM Timer B Match Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIMER_IMR_DMABIM (1 << 13) /* Bit 13: GPTM Timer B DMA Done Interrupt Mask */
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#endif
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_IMR_WUEIM (1 << 16) /* Bit 16: 32/64-Bit Wide GPTM Write Update Error Interrupt Mask */
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#endif
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/* GPTM Raw Interrupt Status (RIS) */
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#define TIMER_RIS_TATORIS (1 << 0) /* Bit 0: Timer A Time-Out Raw Interrupt */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_RIS_CAMRIS (1 << 1) /* Bit 1: GPTM Timer A Capture Mode Match Raw Interrupt */
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# define TIMER_RIS_CAERIS (1 << 2) /* Bit 2: GPTM Timer A Capture Mode Event Raw Interrupt */
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# define TIMER_RIS_RTCRIS (1 << 3) /* Bit 3: GPTM RTC Raw Interrupt */
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# define TIMER_RIS_TAMRIS (1 << 4) /* Bit 4: GPTM Timer A Match Raw Interrupt */
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# define TIMER_INT_DMAB (1 << 13) /* Bit 13: GPTM Timer B DMA Done Interrupt */
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#elif defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_INT_WUE (1 << 16) /* Bit 16: 32/64-Bit Wide GPTM Write Update Error Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIMER_RIS_DMAARIS (1 << 5) /* Bit 5: GPTM Timer A DMA Done Raw Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_RIS_TBTORIS (1 << 8) /* Bit 8: GPTM Timer B Time-Out Raw Interrupt */
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# define TIMER_RIS_CBMRIS (1 << 9) /* Bit 9: GPTM Timer B Capture Mode Match Raw Interrupt */
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# define TIMER_RIS_CBERIS (1 << 10) /* Bit 10: GPTM Timer B Capture Mode Event Raw Interrupt */
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# define TIMER_RIS_TBMRIS (1 << 11) /* Bit 11: GPTM Timer B Match Raw Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIMER_RIS_DMABRIS (1 << 13) /* Bit 13: GPTM Timer B DMA Done Raw Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_RIS_WUERIS (1 << 16) /* Bit 16: 32/64-Bit Wide GPTM Write Update Error Raw Interrupt */
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#endif
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/* GPTM Masked Interrupt Status (MIS) */
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#define TIMER_MIS_TATOMIS (1 << 0) /* Bit 0: Timer A Time-Out Masked Interrupt */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_MIS_CAMMIS (1 << 1) /* Bit 1: GPTM Timer A Capture Mode Match Masked Interrupt */
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# define TIMER_MIS_CAEMIS (1 << 2) /* Bit 2: GPTM Timer A Capture Mode Event Masked Interrupt */
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# define TIMER_MIS_RTCMIS (1 << 3) /* Bit 3: GPTM RTC Masked Interrupt */
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# define TIMER_MIS_TAMMIS (1 << 4) /* Bit 4: GPTM Timer A Match Masked Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIMER_MIS_DMAAMIS (1 << 5) /* Bit 5: GPTM Timer A DMA Done Masked Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_MIS_TBTOMIS (1 << 8) /* Bit 8: GPTM Timer B Time-Out Masked Interrupt */
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# define TIMER_MIS_CBMMIS (1 << 9) /* Bit 9: GPTM Timer B Capture Mode Match Masked Interrupt */
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# define TIMER_MIS_CBEMIS (1 << 10) /* Bit 10: GPTM Timer B Capture Mode Event Masked Interrupt */
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# define TIMER_MIS_TBMMIS (1 << 11) /* Bit 11: GPTM Timer B Match Masked Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIMER_MIS_DMABMIS (1 << 13) /* Bit 13: GPTM Timer B DMA Done Masked Interrupt */
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#endif
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_MIS_WUEMIS (1 << 16) /* Bit 16: 32/64-Bit Wide GPTM Write Update Error Masked Interrupt */
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#endif
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/* GPTM Interrupt Clear (ICR) */
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#define TIMER_ICR_TATOCINT (1 << 0) /* Bit 0: Timer A Time-Out Interrupt Clear */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_ICR_CAMCINT (1 << 1) /* Bit 1: GPTM Timer A Capture Mode Match Interrupt Clear */
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# define TIMER_ICR_CAECINT (1 << 2) /* Bit 2: GPTM Timer A Capture Mode Event Interrupt Clear */
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# define TIMER_ICR_RTCCINT (1 << 3) /* Bit 3: GPTM RTC Interrupt Clear */
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# define TIMER_ICR_TAMCINT (1 << 4) /* Bit 4: GPTM Timer A Match Interrupt Clear */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIMER_ICR_DMAAINT (1 << 5) /* Bit 5: GPTM Timer A DMA Done Interrupt Clear */
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#endif
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_ICR_TBTOCINT (1 << 8) /* Bit 8: GPTM Timer B Time-Out Interrupt Clear */
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# define TIMER_ICR_CBMCINT (1 << 9) /* Bit 9: GPTM Timer B Capture Mode Match Interrupt Clear */
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# define TIMER_ICR_CBECINT (1 << 10) /* Bit 10: GPTM Timer B Capture Mode Event Interrupt Clear */
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# define TIMER_ICR_TBMCINT (1 << 11) /* Bit 11: GPTM Timer B Match Interrupt Clear */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIMER_ICR_DMABINT (1 << 13) /* Bit 13: GPTM Timer B DMA Done Interrupt Clear */
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#endif
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_ICR_WUECINT (1 << 16) /* Bit 16: 32/64-Bit Wide GPTM Write Update Error Interrupt Clear */
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# define TIMERA_INTS 0x0000003f
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# define TIMERB_INTS 0x00002f00
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# define TIMER_ALLINTS 0x00002f3f
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#elif defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMERA_INTS 0x0000001f
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# define TIMERB_INTS 0x00000f00
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# define TIMER_ALLINTS 0x00010f1f
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#else
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# define TIMERA_INTS 0x00000001
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# define TIMERB_INTS 0x00000100
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# define TIMER_ALLINTS 0x00000101
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#endif
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/* GPTM Timer A Interval Load (TAILR) (32-bit value) */
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@ -79,11 +79,15 @@ struct tiva_gptmattr_s
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struct tiva_gptmstate_s
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{
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/* Constant time attributes and configuration */
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/* Constant timer attributes and configuration */
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const struct tiva_gptmattr_s *attr;
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const struct tiva_gptmconfig_s *config;
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/* Variable state values */
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uint32_t imr; /* Interrupt mask value. Zero if no interrupts */
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#ifdef CONFIG_TIVA_TIMER_REGDEBUG
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/* Register level debug */
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@ -394,6 +398,35 @@ static void tiva_putreg(struct tiva_gptmstate_s *priv, unsigned int offset,
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putreg32(regval, regaddr);
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}
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/****************************************************************************
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* Name: tiva_modifyreg
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*
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* Description:
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* This function permits atomic of any timer register by its offset into
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* the timer block. Its primary purpose is to support inline functions
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* defined in this header file.
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*
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****************************************************************************/
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static void tiva_modifyreg(struct tiva_gptmstate_s *priv, unsigned int offset,
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uint32_t clrbits, uint32_t setbits)
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{
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#ifdef CONFIG_TIVA_TIMER_REGDEBUG
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irqstate_t flags;
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uint32_t regval;
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flags = irqsave();
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regval = tiva_getreg(priv, offset);
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regval &= ~clrbits;
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regval |= setbits;
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tiva_putreg(priv, offset, regval);
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irqrestore(flags);
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#else
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uintptr_t regaddr = priv->attr->base + offset;
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modifyreg32(regaddr, clrbits, setbits);
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#endif
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}
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/****************************************************************************
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* Name: tiva_timer32_interrupt
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*
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@ -717,8 +750,25 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
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/* Enable wait-on-trigger? */
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#warning Missing Logic
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/* Enable one-shot/periodic interrupts? */
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#warning Missing Logic
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/* Enable one-shot/periodic interrupts? Enable interrupts only if an
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* interrupt handler was provided.
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*/
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if (timer->handler)
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{
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/* Select the interrupt mask that will enable the timer interrupt.
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* Any non-zero value of imr indicates that interrupts are expected.
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*/
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priv->imr = TIMER_INT_TATO;
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/* Clearing the TACINTD bit allows the time-out interrupt to be
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* generated as normal
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*/
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/* REVISIT: When will interrupts be enabled? */
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regval &= ~TIMER_TnMR_TnCINTD;
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}
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/* Enable count down? */
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@ -747,8 +797,12 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
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/* 6. If interrupts are required, set the appropriate bits in the GPTM
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* Interrupt Mask Register (GPTMIMR).
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*
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* NOTE: Interrupts are still disabled at the NVIC. Interrupts will
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* be enabled at the NVIC after ther timer is started.
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*/
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#warning Missing Logic
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tiva_putreg(priv, TIVA_TIMER_IMR_OFFSET, priv->imr);
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/* 7. Set the TAEN bit in the GPTMCTL register to enable the timer and
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* start counting.
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@ -854,8 +908,25 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv,
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/* Enable wait-on-trigger? */
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#warning Missing Logic
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/* Enable one-shot/periodic interrupts? */
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#warning Missing Logic
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/* Enable one-shot/periodic interrupts? Enable interrupts only if an
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* interrupt handler was provided.
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*/
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if (timer->handler)
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{
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/* Select the interrupt mask that will enable the timer interrupt.
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* Any non-zero value of imr indicates that interrupts are expected.
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*/
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priv->imr |= tmndx ? TIMER_INT_TBTO : TIMER_INT_TATO;
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/* Clearing the TnCINTD bit allows the time-out interrupt to be
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* generated as normal
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*/
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/* REVISIT: When will interrupts be enabled? */
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regval &= ~TIMER_TnMR_TnCINTD;
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}
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/* Enable count down? */
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@ -880,8 +951,12 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv,
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/* 6. If interrupts are required, set the appropriate bits in the GPTM
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* Interrupt Mask Register (GPTMIMR).
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*
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* NOTE: Interrupts are still disabled at the NVIC. Interrupts will
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* be enabled at the NVIC after ther timer is started.
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*/
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#warning Missing Logic
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tiva_putreg(priv, TIVA_TIMER_IMR_OFFSET, priv->imr);
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/* 7. Set the TnEN bit in the GPTMCTL register to enable the timer and
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* start counting.
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@ -1322,7 +1397,10 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config)
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priv->attr = attr;
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priv->config = config;
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/* Detach all interrupt handlers */
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/* Disable and detach all interrupt handlers */
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up_disable_irq(attr->irq[TIMER16A]);
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up_disable_irq(attr->irq[TIMER16B]);
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(void)irq_detach(attr->irq[TIMER16A]);
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(void)irq_detach(attr->irq[TIMER16B]);
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@ -1491,9 +1569,119 @@ void tiva_gptm_modifyreg(TIMER_HANDLE handle, unsigned int offset,
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uint32_t clrbits, uint32_t setbits)
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{
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struct tiva_gptmstate_s *priv = (struct tiva_gptmstate_s *)handle;
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uintptr_t regaddr;
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DEBUGASSERT(priv && priv->attr);
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regaddr = priv->attr->base + offset;
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modifyreg32(regaddr, clrbits, setbits);
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tiva_modifyreg(priv, offset, clrbits, setbits);
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}
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/****************************************************************************
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* Name: tiva_timer32_start
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*
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* Description:
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* After tiva_gptm_configure() has been called to configure a 32-bit timer,
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* this function must be called to start the timer(s).
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*
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****************************************************************************/
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void tiva_timer32_start(TIMER_HANDLE handle)
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{
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struct tiva_gptmstate_s *priv = (struct tiva_gptmstate_s *)handle;
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DEBUGASSERT(priv && priv->attr);
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/* Set the TAEN bit in the GPTMCTL register to enable the 32-bit timer and
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* start counting
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*/
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tiva_modifyreg(priv, TIVA_TIMER_CTL_OFFSET, 0, TIMER_CTL_TAEN);
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/* Enable interrupts at the NVIC if interrupts are expected */
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if (priv->imr)
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{
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up_enable_irq(priv->attr->irq[TIMER32]);
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}
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}
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/****************************************************************************
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* Name: tiva_timer16_start
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*
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* Description:
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* After tiva_gptm_configure() has been called to configure 16-bit timer(s),
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* this function must be called to start one 16-bit timer.
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*
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****************************************************************************/
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void tiva_timer16_start(TIMER_HANDLE handle, int tmndx)
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{
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struct tiva_gptmstate_s *priv = (struct tiva_gptmstate_s *)handle;
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uint32_t setbits;
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uint32_t intmask;
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DEBUGASSERT(priv && priv->attr && (unsigned)tmndx < 2);
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/* Set the TnEN bit in the GPTMCTL register to enable the 16-bit timer and
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* start counting
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*/
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setbits = tmndx ? TIMER_CTL_TBEN : TIMER_CTL_TAEN;
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tiva_modifyreg(priv, TIVA_TIMER_CTL_OFFSET, 0, setbits);
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/* Enable interrupts at the NVIC if interrupts are expected */
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intmask = tmndx ? TIMERB_INTS : TIMERA_INTS;
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if ((priv->imr & intmask) != 0)
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{
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up_enable_irq(priv->attr->irq[tmndx]);
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}
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}
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/****************************************************************************
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* Name: tiva_timer32_stop
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*
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* Description:
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* After tiva_timer32_start() has been called to start a 32-bit timer,
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* this function may be called to stop the timer.
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*
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****************************************************************************/
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void tiva_timer32_stop(TIMER_HANDLE handle)
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{
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struct tiva_gptmstate_s *priv = (struct tiva_gptmstate_s *)handle;
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DEBUGASSERT(priv && priv->attr);
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/* Disable interrupts at the NVIC */
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up_disable_irq(priv->attr->irq[TIMER32]);
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/* Clear the TAEN bit in the GPTMCTL register to disable the 16-bit timer */
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tiva_modifyreg(priv, TIVA_TIMER_CTL_OFFSET, TIMER_CTL_TAEN, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer16_stop
|
||||
*
|
||||
* Description:
|
||||
* After tiva_timer32_start() has been called to start a 16-bit timer,
|
||||
* this function may be called to stop the timer.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_timer16_stop(TIMER_HANDLE handle, int tmndx)
|
||||
{
|
||||
struct tiva_gptmstate_s *priv = (struct tiva_gptmstate_s *)handle;
|
||||
uint32_t clrbits;
|
||||
|
||||
DEBUGASSERT(priv && priv->attr && (unsigned)tmndx < 2);
|
||||
|
||||
/* Disable interrupts at the NVIC */
|
||||
|
||||
up_disable_irq(priv->attr->irq[tmndx]);
|
||||
|
||||
/* Clear the TnEN bit in the GPTMCTL register to disable the 16-bit timer */
|
||||
|
||||
clrbits = tmndx ? TIMER_CTL_TBEN : TIMER_CTL_TAEN;
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, clrbits, 0);
|
||||
}
|
||||
|
||||
@ -301,14 +301,7 @@ void tiva_gptm_modifyreg(TIMER_HANDLE handle, unsigned int offset,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void tiva_timer32_start(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Set the TAEN bit in the GPTMCTL register to enable the timer and start
|
||||
* counting
|
||||
*/
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, 0, TIMER_CTL_TAEN);
|
||||
}
|
||||
void tiva_timer32_start(TIMER_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer16_start
|
||||
@ -319,34 +312,10 @@ static inline void tiva_timer32_start(TIMER_HANDLE handle)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void tiva_timer16_start(TIMER_HANDLE handle, int tmndx)
|
||||
{
|
||||
uint32_t setbits = tmndx ? TIMER_CTL_TBEN : TIMER_CTL_TAEN;
|
||||
void tiva_timer16_start(TIMER_HANDLE handle, int tmndx);
|
||||
|
||||
/* Set the TnEN bit in the GPTMCTL register to enable the 16-bit timer and
|
||||
* start counting
|
||||
*/
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, 0, setbits);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16a_start(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Set the TAEN bit in the GPTMCTL register to enable 16-bit timer A and
|
||||
* start counting
|
||||
*/
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, 0, TIMER_CTL_TAEN);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16b_start(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Set the TBEN bit in the GPTMCTL register to enable 16-bit timer B and
|
||||
* start counting
|
||||
*/
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, 0, TIMER_CTL_TBEN);
|
||||
}
|
||||
#define tiva_timer16a_start(h) tiva_timer16_start(h, TIMER16A)
|
||||
#define tiva_timer16b_start(h) tiva_timer16_start(h, TIMER16B)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer32_stop
|
||||
@ -357,12 +326,7 @@ static inline void tiva_timer16b_start(TIMER_HANDLE handle)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void tiva_timer32_stop(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Clear the TAEN bit in the GPTMCTL register to disable the 16-bit timer */
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, TIMER_CTL_TAEN, 0);
|
||||
}
|
||||
void tiva_timer32_stop(TIMER_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer16_stop
|
||||
@ -373,28 +337,10 @@ static inline void tiva_timer32_stop(TIMER_HANDLE handle)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void tiva_timer16_stop(TIMER_HANDLE handle, int tmndx)
|
||||
{
|
||||
uint32_t clrbits = tmndx ? TIMER_CTL_TBEN : TIMER_CTL_TAEN;
|
||||
void tiva_timer16_stop(TIMER_HANDLE handle, int tmndx);
|
||||
|
||||
/* Clear the TnEN bit in the GPTMCTL register to disable the 16-bit timer */
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, clrbits, 0);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16a_stop(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Clear the TAEN bit in the GPTMCTL register to disable the 16-bit timer A */
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, TIMER_CTL_TAEN, 0);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16b_stop(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Clear the TBEN bit in the GPTMCTL register to disable the 16-bit timer B */
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, TIMER_CTL_TBEN, 0);
|
||||
}
|
||||
#define tiva_timer16a_stop(h) tiva_timer16_stop(h, TIMER16A)
|
||||
#define tiva_timer16b_stop(h) tiva_timer16_stop(h, TIMER16B)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer32_setload
|
||||
|
||||
Loading…
Reference in New Issue
Block a user