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SAMV7: Update floating point and TCM configuration options. Update TODO list. Update comments. Refresh a configuration

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This commit is contained in:
Gregory Nutt 2015-03-10 07:50:32 -06:00
parent 1e0bdf2bc9
commit 95750df002
3 changed files with 17 additions and 5 deletions
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8
configs/samv71-xult/nsh/defconfig
View File

@ -110,7 +110,9 @@ CONFIG_ARCH_CHIP="samv7"
CONFIG_ARCH_HAVE_CMNVECTOR=y
CONFIG_ARMV7M_CMNVECTOR=y
# CONFIG_ARMV7M_LAZYFPU is not set
# CONFIG_ARCH_HAVE_FPU is not set
CONFIG_ARCH_HAVE_FPU=y
CONFIG_ARCH_HAVE_DPFPU=y
# CONFIG_ARCH_FPU is not set
# CONFIG_ARMV7M_MPU is not set
#
@ -120,6 +122,10 @@ CONFIG_ARMV7M_HAVE_ICACHE=y
CONFIG_ARMV7M_HAVE_DCACHE=y
# CONFIG_ARMV7M_ICACHE is not set
# CONFIG_ARMV7M_DCACHE is not set
CONFIG_ARMV7M_HAVE_ITCM=y
CONFIG_ARMV7M_HAVE_DTCM=y
# CONFIG_ARMV7M_ITCM is not set
# CONFIG_ARMV7M_DTCM is not set
# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set

7
configs/samv71-xult/scripts/flash.ld
View File

@ -34,11 +34,14 @@
****************************************************************************/
/* The SAMV71Q21 has 2048Kb of FLASH beginning at address 0x0400:0000 and
* 384Kb of SRAM beginining at 0x2000:0000
* 384Kb of SRAM beginining at 0x2040:0000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address range.
* the 0x0400:0000 address range (Assuming that ITCM is not enable).
*
* NOTE: that the DTCM address of 0x2000:0000 is used for SRAM. If DTCM is
* disabled, then the accesses will actually occur on the AHB bus.
*/
MEMORY

7
configs/samv71-xult/scripts/memory.ld
View File

@ -34,11 +34,14 @@
****************************************************************************/
/* The SAMV71Q21 has 2048Kb of FLASH beginning at address 0x0400:0000 and
* 384Kb of SRAM beginining at 0x2000:0000
* 384Kb of SRAM beginining at 0x2040:0000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address range.
* the 0x0400:0000 address range.
*
* NOTE: that the DTCM address of 0x2000:0000 is used for SRAM. If DTCM is
* disabled, then the accesses will actually occur on the AHB bus.
*
* The user space partition will be spanned with a single region of size
* 2**n bytes. The alignment of the user-space region must be the same.