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arch/armv8-r: new config to set SPIs Configuration to edge-triggered

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Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default

Signed-off-by: chao an <anchao@lixiang.com>
This commit is contained in:
chao an 2024-07-11 09:18:12 +08:00 committed by Xiang Xiao
parent 091372069c
commit 95a9facf3a
2 changed files with 16 additions and 2 deletions
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10
arch/arm/src/armv8-r/Kconfig
View File

@ -13,7 +13,7 @@ config ARMV8R_HAVE_GICv3
Selected by the configuration tool if the architecture supports the Selected by the configuration tool if the architecture supports the
Generic Interrupt Controller (GIC) Generic Interrupt Controller (GIC)
if ARMV8R_HAVE_GICv2 if ARMV8R_HAVE_GICv3
config ARMV8R_GIC_EOIMODE config ARMV8R_GIC_EOIMODE
bool bool
@ -22,7 +22,13 @@ config ARMV8R_GIC_EOIMODE
Enable GICC_CTLR.EOImode, this will separates the priority drop and interrupt Enable GICC_CTLR.EOImode, this will separates the priority drop and interrupt
deactivation operations. deactivation operations.
endif # ARMV8R_GIC_EOIMODE config ARMV8R_GIC_SPI_EDGE
bool "Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default"
default n
---help---
Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default.
endif # ARMV8R_HAVE_GICv3
config ARMV8R_MEMINIT config ARMV8R_MEMINIT
bool bool

8
arch/arm/src/armv8-r/arm_gicv3.c
View File

@ -528,7 +528,15 @@ static void gicv3_dist_init(void)
intid += GIC_NUM_CFG_PER_REG) intid += GIC_NUM_CFG_PER_REG)
{ {
idx = intid / GIC_NUM_CFG_PER_REG; idx = intid / GIC_NUM_CFG_PER_REG;
#ifdef CONFIG_ARMV8R_GIC_SPI_EDGE
/* Configure all SPIs as edge-triggered by default */
putreg32(0xaaaaaaaa, ICFGR(base, idx));
#else
/* Configure all SPIs as level-sensitive by default */
putreg32(0, ICFGR(base, idx)); putreg32(0, ICFGR(base, idx));
#endif
} }
/* TODO: Some arrch64 Cortex-A core maybe without security state /* TODO: Some arrch64 Cortex-A core maybe without security state