Change STM32 tickless to use only one timer
This commit is contained in:
Konstantin Berezenko
parent
0ded0f5866
commit
95cbbf552b
@ -2810,31 +2810,22 @@ menu "Timer Configuration"
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if SCHED_TICKLESS
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config STM32_ONESHOT
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bool
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default y
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config STM32_FREERUN
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bool
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default y
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config STM32_TICKLESS_ONESHOT
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int "Tickless one-shot timer channel"
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config STM32_TICKLESS_TIMER
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int "Tickless hardware timer"
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default 2
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range 1 14
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depends on STM32_ONESHOT
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---help---
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If the Tickless OS feature is enabled, the one clock must be
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assigned to provided the one-shot timer needed by the OS.
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If the Tickless OS feature is enabled, then one clock must be
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assigned to provided the timer needed by the OS.
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config STM32_TICKLESS_FREERUN
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int "Tickless free-running timer channel"
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default 5
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range 1 14
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depends on STM32_FREERUN
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config STM32_TICKLESS_CHANNEL
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int "Tickless timer channel"
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default 1
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range 1 4
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---help---
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If the Tickless OS feature is enabled, the one clock must be
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assigned to provided the free-running timer needed by the OS.
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assigned to provided the free-running timer needed by the OS
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and one channel on that clock is needed to handle intervals.
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endif # SCHED_TICKLESS
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@ -2,7 +2,9 @@
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* arch/arm/src/stm32/stm32_tickless.c
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Copyright (C) 2017 Ansync Labs. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Konstantin Berezenko <kpberezenko@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -55,24 +57,19 @@
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*
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****************************************************************************/
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/****************************************************************************
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* SAM34 Timer Usage
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* STM32 Timer Usage
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*
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* This current implementation uses two timers: A one-shot timer to provide
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* the timed events and a free running timer to provide the current time.
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* Since timers are a limited resource, that could be an issue on some
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* systems.
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*
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* We could do the job with a single timer if we were to keep the single
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* timer in a free-running at all times. The STM32 timer/counters have
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* 16-bit/32-bit counters with the capability to generate a compare interrupt
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* when the timer matches a compare value but also to continue counting
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* without stopping (giving another, different interrupt when the timer
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* rolls over from 0xffffffff to zero). So we could potentially just set
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* the compare at the number of ticks you want PLUS the current value of
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* timer. Then you could have both with a single timer: An interval timer
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* and a free-running counter with the same timer!
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*
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* Patches are welcome!
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* This implementation uses one timer: A free running timer to provide
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* the current time and a capture/compare channel for timed-events.
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* The STM32 has both 16-bit and 32-bit timers so to keep things consistent
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* we limit the timer counters to a 16-bit range. BASIC timers that
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* are found on some STM32 chips (timers 6 and 7) are incompatible with this
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* implementation because they don't have capture/compare channels. There
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* are two interrupts generated from our timer, the overflow interrupt which
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* drives the timing handler and the capture/compare interrupt which drives
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* the interval handler. There are some low level timer control functions
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* implemented here because the API of stm32_tim.c does not provide adequate
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* control over capture/compare interrupts.
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*
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****************************************************************************/
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@ -84,12 +81,15 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <assert.h>
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#include <nuttx/arch.h>
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#include <debug.h>
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#include "stm32_oneshot.h"
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#include "stm32_freerun.h"
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#include "up_arch.h"
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#include "stm32_tim.h"
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#ifdef CONFIG_SCHED_TICKLESS
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@ -97,30 +97,24 @@
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef CONFIG_STM32_ONESHOT
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# error CONFIG_STM32_ONESHOT must be selected for the Tickless OS option
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#endif
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#ifndef CONFIG_STM32_FREERUN
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# error CONFIG_STM32_FREERUN must be selected for the Tickless OS option
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#endif
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#ifndef CONFIG_STM32_TICKLESS_FREERUN
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# error CONFIG_STM32_TICKLESS_FREERUN must be selected for the Tickless OS option
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#endif
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#ifndef CONFIG_STM32_TICKLESS_ONESHOT
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# error CONFIG_STM32_TICKLESS_ONESHOT must be selected for the Tickless OS option
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct stm32_tickless_s
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{
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struct stm32_oneshot_s oneshot;
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struct stm32_freerun_s freerun;
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uint8_t timer; /* The timer/counter in use */
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uint8_t channel; /* The timer channel to use for intervals */
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FAR struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */
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uint32_t frequency;
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#ifdef CONFIG_CLOCK_TIMEKEEPING
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uint64_t counter_mask;
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#else
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uint32_t overflow; /* Timer counter overflow */
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#endif
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volatile bool pending; /* True: pending task */
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uint32_t period; /* Interval period */
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uint32_t base;
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};
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/****************************************************************************
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@ -133,11 +127,155 @@ static struct stm32_tickless_s g_tickless;
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_oneshot_handler
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/************************************************************************************
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* Name: stm32_getreg16
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*
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* Description:
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* Called when the one shot timer expires
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* Get a 16-bit register value by offset
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*
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************************************************************************************/
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static inline uint16_t stm32_getreg16(uint8_t offset)
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{
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return getreg16(g_tickless.base + offset);
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}
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/************************************************************************************
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* Name: stm32_putreg16
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*
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* Description:
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* Put a 16-bit register value by offset
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*
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************************************************************************************/
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static inline void stm32_putreg16(uint8_t offset, uint16_t value)
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{
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putreg16(value, g_tickless.base + offset);
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}
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/************************************************************************************
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* Name: stm32_modifyreg16
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*
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* Description:
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* Modify a 16-bit register value by offset
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*
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************************************************************************************/
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static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits, uint16_t setbits)
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{
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modifyreg16(g_tickless.base + offset, clearbits, setbits);
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}
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/************************************************************************************
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* Name: stm32_tickless_enableint
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************************************************************************************/
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static inline void stm32_tickless_enableint(int channel)
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{
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stm32_modifyreg16(STM32_BTIM_DIER_OFFSET, 0, 1 << channel);
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}
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/************************************************************************************
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* Name: stm32_tickless_disableint
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************************************************************************************/
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static inline void stm32_tickless_disableint(int channel)
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{
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stm32_modifyreg16(STM32_BTIM_DIER_OFFSET, 1 << channel, 0);
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}
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/************************************************************************************
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* Name: stm32_tickless_ackint
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************************************************************************************/
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static inline void stm32_tickless_ackint(int channel)
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{
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stm32_putreg16(STM32_BTIM_SR_OFFSET, ~(1 << channel));
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}
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/************************************************************************************
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* Name: stm32_tickless_getint
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************************************************************************************/
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static inline uint16_t stm32_tickless_getint(void)
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{
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return stm32_getreg16(STM32_BTIM_SR_OFFSET);
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}
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/************************************************************************************
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* Name: stm32_tickless_setchannel
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************************************************************************************/
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static int stm32_tickless_setchannel(uint8_t channel)
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{
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uint16_t ccmr_orig = 0;
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uint16_t ccmr_val = 0;
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uint16_t ccmr_mask = 0xff;
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uint16_t ccer_val = stm32_getreg16(STM32_GTIM_CCER_OFFSET);
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uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
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/* Further we use range as 0..3; if channel=0 it will also overflow here */
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if (--channel > 4)
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{
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return -EINVAL;
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}
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/* Assume that channel is disabled and polarity is active high */
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ccer_val &= ~(3 << (channel << 2));
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/* This function is not supported on basic timers. To enable or
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* disable it, simply set its clock to valid frequency or zero.
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*/
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#if STM32_NBTIM > 0
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if (g_tickless.base == STM32_TIM6_BASE
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#endif
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#if STM32_NBTIM > 1
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|| g_tickless.base == STM32_TIM7_BASE
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#endif
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#if STM32_NBTIM > 0
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)
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{
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return -EINVAL;
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}
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#endif
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/* frozen mode because we don't want to change the gpio, preload register disabled */
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ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT);
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/* Set polarity */
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ccer_val |= ATIM_CCER_CC1P << (channel << 2);
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/* Define its position (shift) and get register offset */
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if (channel & 1)
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{
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ccmr_val <<= 8;
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ccmr_mask <<= 8;
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}
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if (channel > 1)
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{
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ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
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}
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ccmr_orig = stm32_getreg16(ccmr_offset);
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ccmr_orig &= ~ccmr_mask;
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ccmr_orig |= ccmr_val;
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stm32_putreg16(ccmr_offset, ccmr_orig);
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stm32_putreg16(STM32_GTIM_CCER_OFFSET, ccer_val);
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return OK;
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}
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/****************************************************************************
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* Name: stm32_interval_handler
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*
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* Description:
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* Called when the timer counter matches the compare register
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*
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* Input Parameters:
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* None
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@ -151,12 +289,76 @@ static struct stm32_tickless_s g_tickless;
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*
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****************************************************************************/
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static void stm32_oneshot_handler(void *arg)
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static void stm32_interval_handler(void)
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{
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tmrinfo("Expired...\n");
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/* Disable the compare interrupt now. */
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stm32_tickless_disableint(g_tickless.channel);
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stm32_tickless_ackint(g_tickless.channel);
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g_tickless.pending = false;
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sched_timer_expiration();
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}
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/****************************************************************************
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* Name: stm32_timing_handler
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*
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* Description:
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* Timer interrupt callback. When the freerun timer counter overflows,
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* this interrupt will occur. We will just increment an overflow count.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifndef CONFIG_CLOCK_TIMEKEEPING
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static void stm32_timing_handler(void)
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{
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g_tickless.overflow++;
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STM32_TIM_ACKINT(g_tickless.tch, 0);
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}
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#endif /* CONFIG_CLOCK_TIMEKEEPING */
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/****************************************************************************
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* Name: stm32_tickless_handler
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*
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* Description:
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* Generic interrupt handler for this timer. It checks the source of the
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* interrupt and fires the appropriate handler.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static int stm32_tickless_handler(int irq, void *context, void *arg)
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{
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int interrupt_flags = stm32_tickless_getint();
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#ifndef CONFIG_CLOCK_TIMEKEEPING
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if (interrupt_flags & ATIM_SR_UIF)
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stm32_timing_handler();
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#endif /* CONFIG_CLOCK_TIMEKEEPING */
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if (interrupt_flags & (1 << g_tickless.channel))
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stm32_interval_handler();
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -188,55 +390,162 @@ static void stm32_oneshot_handler(void *arg)
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void arm_timer_initialize(void)
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{
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#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
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uint64_t max_delay;
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switch (CONFIG_STM32_TICKLESS_TIMER)
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{
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#ifdef CONFIG_STM32_TIM1
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case 1:
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g_tickless.base = STM32_TIM1_BASE;
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break;
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#endif
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int ret;
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#ifdef CONFIG_STM32_TIM2
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case 2:
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g_tickless.base = STM32_TIM2_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM3
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case 3:
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g_tickless.base = STM32_TIM3_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM4
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case 4:
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g_tickless.base = STM32_TIM4_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM5
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case 5:
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g_tickless.base = STM32_TIM5_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM6
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case 6:
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/* Initialize the one-shot timer */
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/* Basic timers not supported by this implementation */
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ret = stm32_oneshot_initialize(&g_tickless.oneshot,
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CONFIG_STM32_TICKLESS_ONESHOT,
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CONFIG_USEC_PER_TICK);
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if (ret < 0)
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{
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tmrerr("ERROR: stm32_oneshot_initialize failed\n");
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PANIC();
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}
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ASSERT(0);
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break;
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#endif
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#ifdef CONFIG_STM32_TIM7
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case 7:
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#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
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/* Get the maximum delay of the one-shot timer in microseconds */
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/* Basic timers not supported by this implementation */
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ret = stm32_oneshot_max_delay(&g_tickless.oneshot, &max_delay);
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if (ret < 0)
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{
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tmrerr("ERROR: stm32_oneshot_max_delay failed\n");
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PANIC();
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}
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/* Convert this to configured clock ticks for use by the OS timer logic */
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max_delay /= CONFIG_USEC_PER_TICK;
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if (max_delay > UINT32_MAX)
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{
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g_oneshot_maxticks = UINT32_MAX;
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}
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else
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{
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g_oneshot_maxticks = max_delay;
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}
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ASSERT(0);
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break;
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#endif
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#ifdef CONFIG_STM32_TIM8
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case 8:
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g_tickless.base = STM32_TIM8_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM9
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case 9:
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g_tickless.base = STM32_TIM9_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM10
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case 10:
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g_tickless.base = STM32_TIM10_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM11
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case 11:
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g_tickless.base = STM32_TIM11_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM12
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case 12:
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g_tickless.base = STM32_TIM12_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM13
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case 13:
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g_tickless.base = STM32_TIM13_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM14
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case 14:
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g_tickless.base = STM32_TIM14_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM15
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case 15:
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g_tickless.base = STM32_TIM15_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM16
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case 16:
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g_tickless.base = STM32_TIM16_BASE;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM17
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case 17:
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g_tickless.base = STM32_TIM17_BASE;
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break;
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#endif
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|
||||
/* Initialize the free-running timer */
|
||||
default:
|
||||
ASSERT(0);
|
||||
|
||||
ret = stm32_freerun_initialize(&g_tickless.freerun,
|
||||
CONFIG_STM32_TICKLESS_FREERUN,
|
||||
CONFIG_USEC_PER_TICK);
|
||||
if (ret < 0)
|
||||
{
|
||||
tmrerr("ERROR: stm32_freerun_initialize failed\n");
|
||||
PANIC();
|
||||
}
|
||||
|
||||
/* Get the TC frequency that corresponds to the requested resolution */
|
||||
|
||||
g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK;
|
||||
g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER;
|
||||
g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL;
|
||||
g_tickless.pending = false;
|
||||
g_tickless.period = 0;
|
||||
|
||||
tmrinfo("timer=%d channel=%d frequency=%d Hz\n",
|
||||
g_tickless.timer, g_tickless.channel, g_tickless.frequency);
|
||||
|
||||
g_tickless.tch = stm32_tim_init(g_tickless.timer);
|
||||
if (!g_tickless.tch)
|
||||
{
|
||||
tmrerr("ERROR: Failed to allocate TIM%d\n", g_tickless.timer);
|
||||
ASSERT(0);
|
||||
}
|
||||
|
||||
STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency);
|
||||
|
||||
#ifdef CONFIG_CLOCK_TIMEKEEPING
|
||||
|
||||
/* Should this be changed to 0xffff because we use 16 bit timers? */
|
||||
|
||||
g_tickless.counter_mask = 0xffffffffull;
|
||||
#else
|
||||
g_tickless.overflow = 0;
|
||||
|
||||
/* Set up to receive the callback when the counter overflow occurs */
|
||||
|
||||
STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0);
|
||||
#endif
|
||||
|
||||
/* Initialize interval to zero */
|
||||
|
||||
STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0);
|
||||
|
||||
/* Setup compare channel for the interval timing */
|
||||
|
||||
stm32_tickless_setchannel(g_tickless.channel);
|
||||
|
||||
/* Set timer period */
|
||||
|
||||
STM32_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX);
|
||||
|
||||
/* Initialize the counter */
|
||||
|
||||
STM32_TIM_SETMODE(g_tickless.tch, STM32_TIM_MODE_UP);
|
||||
|
||||
#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
|
||||
g_oneshot_maxticks = UINT16_MAX;
|
||||
#endif
|
||||
|
||||
/* Start the timer */
|
||||
|
||||
STM32_TIM_ACKINT(g_tickless.tch, 0);
|
||||
STM32_TIM_ENABLEINT(g_tickless.tch, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -276,14 +585,84 @@ void arm_timer_initialize(void)
|
||||
|
||||
int up_timer_gettime(FAR struct timespec *ts)
|
||||
{
|
||||
return stm32_freerun_counter(&g_tickless.freerun, ts);
|
||||
uint64_t usec;
|
||||
uint32_t counter;
|
||||
uint32_t verify;
|
||||
uint32_t overflow;
|
||||
uint32_t sec;
|
||||
int pending;
|
||||
irqstate_t flags;
|
||||
|
||||
DEBUGASSERT(g_tickless.tch && ts);
|
||||
|
||||
/* Temporarily disable the overflow counter. NOTE that we have to be
|
||||
* careful here because stm32_tc_getpending() will reset the pending
|
||||
* interrupt status. If we do not handle the overflow here then, it will
|
||||
* be lost.
|
||||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
overflow = g_tickless.overflow;
|
||||
counter = STM32_TIM_GETCOUNTER(g_tickless.tch);
|
||||
pending = STM32_TIM_CHECKINT(g_tickless.tch, 0);
|
||||
verify = STM32_TIM_GETCOUNTER(g_tickless.tch);
|
||||
|
||||
/* If an interrupt was pending before we re-enabled interrupts,
|
||||
* then the overflow needs to be incremented.
|
||||
*/
|
||||
|
||||
if (pending)
|
||||
{
|
||||
STM32_TIM_ACKINT(g_tickless.tch, 0);
|
||||
|
||||
/* Increment the overflow count and use the value of the
|
||||
* guaranteed to be AFTER the overflow occurred.
|
||||
*/
|
||||
|
||||
overflow++;
|
||||
counter = verify;
|
||||
|
||||
/* Update tickless overflow counter. */
|
||||
|
||||
g_tickless.overflow = overflow;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
tmrinfo("counter=%lu (%lu) overflow=%lu, pending=%i\n",
|
||||
(unsigned long)counter, (unsigned long)verify,
|
||||
(unsigned long)overflow, pending);
|
||||
tmrinfo("frequency=%u\n", g_tickless.frequency);
|
||||
|
||||
/* Convert the whole thing to units of microseconds.
|
||||
*
|
||||
* frequency = ticks / second
|
||||
* seconds = ticks * frequency
|
||||
* usecs = (ticks * USEC_PER_SEC) / frequency;
|
||||
*/
|
||||
|
||||
usec = ((((uint64_t)overflow << 16) + (uint64_t)counter) * USEC_PER_SEC) /
|
||||
g_tickless.frequency;
|
||||
|
||||
/* And return the value of the timer */
|
||||
|
||||
sec = (uint32_t)(usec / USEC_PER_SEC);
|
||||
ts->tv_sec = sec;
|
||||
ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
|
||||
|
||||
tmrinfo("usec=%llu ts=(%u, %lu)\n",
|
||||
usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
int up_timer_getcounter(FAR uint64_t *cycles)
|
||||
{
|
||||
return stm32_freerun_counter(&g_tickless.freerun, cycles);
|
||||
*cycles = (uint64_t)STM32_TIM_GETCOUNTER(g_tickless.tch);
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CLOCK_TIMEKEEPING */
|
||||
@ -306,7 +685,7 @@ int up_timer_getcounter(FAR uint64_t *cycles)
|
||||
void up_timer_getmask(FAR uint64_t *mask)
|
||||
{
|
||||
DEBUGASSERT(mask != NULL);
|
||||
*mask = g_tickless.freerun.counter_mask;
|
||||
*mask = g_tickless.counter_mask;
|
||||
}
|
||||
#endif /* CONFIG_CLOCK_TIMEKEEPING */
|
||||
|
||||
@ -348,7 +727,100 @@ void up_timer_getmask(FAR uint64_t *mask)
|
||||
|
||||
int up_timer_cancel(FAR struct timespec *ts)
|
||||
{
|
||||
return stm32_oneshot_cancel(&g_tickless.oneshot, ts);
|
||||
irqstate_t flags;
|
||||
uint64_t usec;
|
||||
uint64_t sec;
|
||||
uint64_t nsec;
|
||||
uint32_t count;
|
||||
uint32_t period;
|
||||
|
||||
/* Was the timer running? */
|
||||
|
||||
flags = enter_critical_section();
|
||||
if (!g_tickless.pending)
|
||||
{
|
||||
/* No.. Just return zero timer remaining and successful cancellation.
|
||||
* This function may execute at a high rate with no timer running
|
||||
* (as when pre-emption is enabled and disabled).
|
||||
*/
|
||||
|
||||
if (ts)
|
||||
{
|
||||
ts->tv_sec = 0;
|
||||
ts->tv_nsec = 0;
|
||||
}
|
||||
leave_critical_section(flags);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/* Yes.. Get the timer counter and period registers and disable the compare interrupt.
|
||||
*
|
||||
*/
|
||||
|
||||
tmrinfo("Cancelling...\n");
|
||||
|
||||
/* Disable the interrupt. */
|
||||
|
||||
stm32_tickless_disableint(g_tickless.channel);
|
||||
|
||||
count = STM32_TIM_GETCOUNTER(g_tickless.tch);
|
||||
period = g_tickless.period;
|
||||
|
||||
g_tickless.pending = false;
|
||||
leave_critical_section(flags);
|
||||
|
||||
/* Did the caller provide us with a location to return the time
|
||||
* remaining?
|
||||
*/
|
||||
|
||||
if (ts)
|
||||
{
|
||||
/* Yes.. then calculate and return the time remaining on the
|
||||
* oneshot timer.
|
||||
*/
|
||||
|
||||
tmrinfo("period=%lu count=%lu\n",
|
||||
(unsigned long)period, (unsigned long)count);
|
||||
|
||||
if (count > period)
|
||||
{
|
||||
/* Handle rollover */
|
||||
|
||||
period += UINT16_MAX;
|
||||
}
|
||||
else if (count == period)
|
||||
{
|
||||
/* No time remaining */
|
||||
|
||||
ts->tv_sec = 0;
|
||||
ts->tv_nsec = 0;
|
||||
return OK;
|
||||
}
|
||||
|
||||
/* The total time remaining is the difference. Convert that
|
||||
* to units of microseconds.
|
||||
*
|
||||
* frequency = ticks / second
|
||||
* seconds = ticks * frequency
|
||||
* usecs = (ticks * USEC_PER_SEC) / frequency;
|
||||
*/
|
||||
|
||||
usec = (((uint64_t)(period - count)) * USEC_PER_SEC) /
|
||||
g_tickless.frequency;
|
||||
|
||||
/* Return the time remaining in the correct form */
|
||||
|
||||
sec = usec / USEC_PER_SEC;
|
||||
nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
|
||||
|
||||
ts->tv_sec = (time_t)sec;
|
||||
ts->tv_nsec = (unsigned long)nsec;
|
||||
|
||||
tmrinfo("remaining (%lu, %lu)\n",
|
||||
(unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -378,6 +850,64 @@ int up_timer_cancel(FAR struct timespec *ts)
|
||||
|
||||
int up_timer_start(FAR const struct timespec *ts)
|
||||
{
|
||||
return stm32_oneshot_start(&g_tickless.oneshot, stm32_oneshot_handler, NULL, ts);
|
||||
uint64_t usec;
|
||||
uint64_t period;
|
||||
uint32_t count;
|
||||
irqstate_t flags;
|
||||
|
||||
tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n",
|
||||
handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
|
||||
DEBUGASSERT(ts);
|
||||
DEBUGASSERT(g_tickless.tch);
|
||||
|
||||
/* Was an interval already running? */
|
||||
|
||||
flags = enter_critical_section();
|
||||
if (g_tickless.pending)
|
||||
{
|
||||
/* Yes.. then cancel it */
|
||||
|
||||
tmrinfo("Already running... cancelling\n");
|
||||
(void)up_timer_cancel(NULL);
|
||||
}
|
||||
|
||||
/* Express the delay in microseconds */
|
||||
|
||||
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
|
||||
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
|
||||
|
||||
/* Get the timer counter frequency and determine the number of counts need
|
||||
* to achieve the requested delay.
|
||||
*
|
||||
* frequency = ticks / second
|
||||
* ticks = seconds * frequency
|
||||
* = (usecs * frequency) / USEC_PER_SEC;
|
||||
*/
|
||||
|
||||
period = (usec * (uint64_t)g_tickless.frequency) / USEC_PER_SEC;
|
||||
count = STM32_TIM_GETCOUNTER(g_tickless.tch);
|
||||
|
||||
tmrinfo("usec=%llu period=%08llx\n", usec, period);
|
||||
DEBUGASSERT(period <= UINT16_MAX);
|
||||
|
||||
/* Set interval compare value. Rollover is fine,
|
||||
* channel will trigger on the next period. (uint16_t) cast
|
||||
* handles the overflow.
|
||||
*/
|
||||
|
||||
g_tickless.period = (uint16_t)(period + count);
|
||||
|
||||
STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, g_tickless.period);
|
||||
|
||||
/* Enable interrupts. We should get the callback when the interrupt
|
||||
* occurs.
|
||||
*/
|
||||
|
||||
stm32_tickless_ackint(g_tickless.channel);
|
||||
stm32_tickless_enableint(g_tickless.channel);
|
||||
|
||||
g_tickless.pending = true;
|
||||
leave_critical_section(flags);
|
||||
return OK;
|
||||
}
|
||||
#endif /* CONFIG_SCHED_TICKLESS */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user