With these changes, I am able to access NSH on Beaglebone Black.

I still observe data abort crash if I compile the code with optimization enabled.

The next steps are to investigate the optimization issue and add Watchdog module. Currently, NSH does not run for a long time ;)

  arch/arm/src/am335x/am335x_irq.c:  Correct interrupt processing routine
  configs/beaglebone-black/nsh/defconfig:  Enable debug compilation options. Otherwise data abort crash is observed
  arch/arm/src/am335x/am335x_lowputc.c and arch/arm/src/am335x/chip/am335x_uart.h:  UART-related cosmetic changes
  arch/arm/src/am335x/am335x_timerisr.c:  Make sure that Timer 1 interrupts are disabled before any access to peripheral registers

arch/arm/src/am335x/am335x_irq.c

@@ -173,11 +173,19 @@ uint32_t *arm_decodeirq(uint32_t *regs)
 #if 1 /* Use PEND registers instead */
   uint32_t regval;
 
+  /* Get active interrupt line */
+
   regval = getreg32(AM335X_INTC_SIR_IRQ) & INTC_SIR_IRQ_ACTIVE_MASK;
 
   /* Dispatch the interrupt */
 
-  return arm_doirq((int)regval, regs);
+  regs = arm_doirq((int)regval, regs);
+
+  /* Enable new interrupt generation */
+
+  putreg32(INTC_CONTROL_NEWIRQAGR, AM335X_INTC_CONTROL);
+
+  return regs;
 #else
   uintptr_t regaddr;
   uint32_t pending;

arch/arm/src/am335x/am335x_lowputc.c

@@ -231,10 +231,12 @@ void am335x_lowsetup(void)
 
   putreg32(UART_SYSC_SRESET | getreg32(CONSOLE_BASE + AM335X_UART_SYSC_OFFSET),
           CONSOLE_BASE + AM335X_UART_SYSC_OFFSET);
-#endif
 
   /* Wait until the process of Module Reset is complete. */
-  //while(!(getreg32(CONSOLE_BASE + AM335X_UART_SYSS_OFFSET) & 1));
+  while (!(getreg32(CONSOLE_BASE + AM335X_UART_SYSS_OFFSET) & UART_SYSS_RESET_DONE))
+    {
+    }
+#endif
 
   /* Put UART to disabled mode */
 

arch/arm/src/am335x/am335x_timerisr.c

@@ -118,6 +118,20 @@ void arm_timer_initialize(void)
 {
   uint32_t regval;
 
+  /* Make sure that interrupts from the Timer 1 are disabled */
+
+  up_disable_irq(AM335X_IRQ_TIMER1_1MS);
+
+#if 0
+  /* Soft reset the timer */
+
+  putreg32(TMR1MS_TIOCP_SOFT_RESET, AM335X_TMR1MS_TIOCP_CFG);
+
+  while (!(getreg32(AM335X_TMR1MS_TISTAT) & TMR1MS_TISTAT))
+    {
+    }
+#endif
+
   /* Stop timer */
 
   putreg32(0, AM335X_TMR1MS_TCLR);
@@ -133,10 +147,6 @@ void arm_timer_initialize(void)
            TMR1MS_TCLR_ST;
   putreg32(regval, AM335X_TMR1MS_TCLR);
 
-  /* Make sure that interrupts from the Timer 0 are disabled */
-
-  up_disable_irq(AM335X_IRQ_TIMER1_1MS);
-
   /* Attach the timer interrupt vector */
 
   (void)irq_attach(AM335X_IRQ_TIMER1_1MS, (xcpt_t)am335x_timerisr, NULL);

arch/arm/src/am335x/chip/am335x_timer.h

@@ -63,9 +63,9 @@
 #define AM335X_TMR_TTGR_OFFSET          0x0044 /* Timer Trigger Register */
 #define AM335X_TMR_TWPS_OFFSET          0x0048 /* Timer Write Posting Bits Register */
 #define AM335X_TMR_TMAR_OFFSET          0x004C /* Timer Match Register */
-#define AM335X_TMR_TCAR1_OFFSET         0x0050 /* Timer Capture Register */
+#define AM335X_TMR_TCAR1_OFFSET         0x0050 /* Timer Capture 1 Register */
 #define AM335X_TMR_TSICR_OFFSET         0x0054 /* Timer Synchronous Interface Control Register */
-#define AM335X_TMR_TCAR2_OFFSET         0x0058 /* Timer Capture Register */
+#define AM335X_TMR_TCAR2_OFFSET         0x0058 /* Timer Capture 2 Register */
 
 #define AM335X_TMR1MS_TIDR_OFFSET       0x0000 /* Identification Register Section */
 #define AM335X_TMR1MS_TIOCP_CFG_OFFSET  0x0010 /* 1ms Timer OCP Configuration Register Section */
@@ -79,9 +79,9 @@
 #define AM335X_TMR1MS_TTGR_OFFSET       0x0030 /* 1ms Timer Trigger Register */
 #define AM335X_TMR1MS_TWPS_OFFSET       0x0034 /* 1ms Timer Write Posting Bits Register */
 #define AM335X_TMR1MS_TMAR_OFFSET       0x0038 /* 1ms Timer Match Register */
-#define AM335X_TMR1MS_TCAR1_OFFSET      0x003C /* 1ms Timer Capture Register */
+#define AM335X_TMR1MS_TCAR1_OFFSET      0x003C /* 1ms Timer Capture 1 Register */
 #define AM335X_TMR1MS_TSICR_OFFSET      0x0040 /* 1ms Timer Synchronous Interface Control Register */
-#define AM335X_TMR1MS_TCAR2_OFFSET      0x0044 /* 1ms Timer Capture Register */
+#define AM335X_TMR1MS_TCAR2_OFFSET      0x0044 /* 1ms Timer Capture 2 Register */
 #define AM335X_TMR1MS_TPIR_OFFSET       0x0048 /* 1ms Timer Positive Increment Register */
 #define AM335X_TMR1MS_TNIR_OFFSET       0x004C /* 1ms Timer Negative Increment Register */
 #define AM335X_TMR1MS_TCVR_OFFSET       0x0050 /* 1ms Timer Counter Value Register */
@@ -90,6 +90,8 @@
 
 /* Register virtual addresses *******************************************************/
 
+#define AM335X_TMR1MS_TIOCP_CFG         (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TIOCP_CFG_OFFSET)
+#define AM335X_TMR1MS_TISTAT            (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TISTAT_OFFSET)
 #define AM335X_TMR1MS_TISR              (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TISR_OFFSET)
 #define AM335X_TMR1MS_TIER              (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TIER_OFFSET)
 #define AM335X_TMR1MS_TCLR              (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TCLR_OFFSET)

arch/arm/src/am335x/chip/am335x_uart.h

@@ -391,6 +391,10 @@
 #define UART_SYSC_SRESET            (1 << 1)  /* Bit 1: Software Reset */
 #define UART_SYSC_WAKEUP            (1 << 2)  /* Bit 2: Wake-up Control */
 
+/* UART System Status Register */
+
+#define UART_SYSS_RESET_DONE        (1 << 0)  /* Bit 0: Reset Complete */
+
 /* UART Enhanced Feature Register */
 
 #define UART_EFR_ENHANCEDEN         (1 << 4)  /* Bit 4: Enable Enhanced Functions Write */

configs/beaglebone-black/nsh/defconfig

@@ -13,6 +13,9 @@ CONFIG_ARCH_LOWVECTORS=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARCH="arm"
 CONFIG_BOARD_LOOPSPERMSEC=49341
+CONFIG_DEBUG_CUSTOMOPT=y
+CONFIG_DEBUG_OPTLEVEL="-O0"
+CONFIG_DEBUG_SYMBOLS=y
 CONFIG_BOOT_RUNFROMSDRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y