arch/arm/src/s32k1xx: A few fixes. The build progresses further but still fails.
This commit is contained in:
Gregory Nutt
parent
50a333f55c
commit
963031f42c
@ -57,59 +57,59 @@
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/* Processor Exceptions (vectors 0-15) */
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#define S32K_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vector 4-10: Reserved */
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#define S32K_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define S32K_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K_IRQ_SYSTICK (15) /* Vector 15: System tick */
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#define S32K1XX_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K1XX_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K1XX_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vector 4-10: Reserved */
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#define S32K1XX_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define S32K1XX_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K1XX_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16). These definitions are chip-specific */
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#define S32K_IRQ_INTERRUPT (16)
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#define S32K1XX_IRQ_INTERRUPT (16)
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#define S32K_IRQ_DMACH0 (16) /* DMA channel 0 transfer complete */
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#define S32K_IRQ_DMACH1 (17) /* DMA channel 1 transfer complete */
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#define S32K_IRQ_DMACH2 (18) /* DMA channel 2 transfer complete */
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#define S32K_IRQ_DMACH3 (19) /* DMA channel 3 transfer complete */
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#define S32K_IRQ_DMACH_ERR (20) /* DMA error interrupt channels 0-15 */
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#define S32K_IRQ_ERM (21) /* ERM single/double bit error */
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#define S32K_IRQ_RTC_ALARM (22) /* RTC alarm interrupt */
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#define S32K_IRQ_RTC_SEC (23) /* RTC seconds interrupt */
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#define S32K_IRQ_LPTIMER (24) /* LPTIMER interrupt request */
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#define S32K_IRQ_PORT (25) /* PORTA-E Interrupt */
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#define S32K_IRQ_CAN0 (26) /* CAN0 OR'ed Interrupt */
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#define S32K_IRQ_CAN0_0_31 (27) /* CAN0 OR'ed Message buffer (0-31) */
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#define S32K_IRQ_FTM0_CH0_7 (28) /* FTM0 Channel 0..7 Interrupt */
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#define S32K_IRQ_FTM0_FAULT (29) /* FTM0 Fault Interrupt */
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#define S32K_IRQ_FTM0_OVERFLOW (30) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM1_CH0_7 (31) /* FTM1 Channel 0..7 Interrupt */
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#define S32K_IRQ_FTM1_FAULT (32) /* FTM1 Fault Interrupt */
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#define S32K_IRQ_FTM1_OVERFLOW (33) /* FTM1 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTFC (34) /* FTFC Command Complete, Collision, Double bit */
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#define S32K_IRQ_PDB (35) /* PDB Interrupt */
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#define S32K_IRQ_LPIT (36) /* LPIT Interrupt */
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#define S32K_IRQ_PMC (37) /* PMC Interrupt */
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#define S32K_IRQ_WDOG (38) /* WDOG interrupt request out before wdg reset out */
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#define S32K_IRQ_RCM (39) /* RCM Asynchronous Interrupt */
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#define S32K_IRQ_LPI2C0 (40) /* LPI2C Master/Slave Interrupt */
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#define S32K_IRQ_FLEXIO (41) /* FlexIO Interrupt */
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#define S32K_IRQ_LPSPI0 (42) /* LPSPI0 Interrupt */
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#define S32K_IRQ_LPSPI1 (43) /* LPSPI1 Interrupt */
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#define S32K_IRQ_ADC0 (44) /* ADC0 Interrupt */
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#define S32K_IRQ_CMP0 (45) /* CMP0 Interrupt */
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#define S32K_IRQ_LPUART1 (46) /* LPUART1 Interrupt */
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#define S32K_IRQ_LPUART1 (47) /* LPUART0 Interrupt */
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#define S32K1XX_IRQ_DMACH0 (16) /* DMA channel 0 transfer complete */
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#define S32K1XX_IRQ_DMACH1 (17) /* DMA channel 1 transfer complete */
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#define S32K1XX_IRQ_DMACH2 (18) /* DMA channel 2 transfer complete */
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#define S32K1XX_IRQ_DMACH3 (19) /* DMA channel 3 transfer complete */
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#define S32K1XX_IRQ_DMACH_ERR (20) /* DMA error interrupt channels 0-15 */
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#define S32K1XX_IRQ_ERM (21) /* ERM single/double bit error */
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#define S32K1XX_IRQ_RTC_ALARM (22) /* RTC alarm interrupt */
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#define S32K1XX_IRQ_RTC_SEC (23) /* RTC seconds interrupt */
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#define S32K1XX_IRQ_LPTIMER (24) /* LPTIMER interrupt request */
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#define S32K1XX_IRQ_PORT (25) /* PORTA-E Interrupt */
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#define S32K1XX_IRQ_CAN0 (26) /* CAN0 OR'ed Interrupt */
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#define S32K1XX_IRQ_CAN0_0_31 (27) /* CAN0 OR'ed Message buffer (0-31) */
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#define S32K1XX_IRQ_FTM0_CH0_7 (28) /* FTM0 Channel 0..7 Interrupt */
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#define S32K1XX_IRQ_FTM0_FAULT (29) /* FTM0 Fault Interrupt */
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#define S32K1XX_IRQ_FTM0_OVERFLOW (30) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTM1_CH0_7 (31) /* FTM1 Channel 0..7 Interrupt */
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#define S32K1XX_IRQ_FTM1_FAULT (32) /* FTM1 Fault Interrupt */
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#define S32K1XX_IRQ_FTM1_OVERFLOW (33) /* FTM1 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTFC (34) /* FTFC Command Complete, Collision, Double bit */
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#define S32K1XX_IRQ_PDB (35) /* PDB Interrupt */
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#define S32K1XX_IRQ_LPIT (36) /* LPIT Interrupt */
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#define S32K1XX_IRQ_PMC (37) /* PMC Interrupt */
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#define S32K1XX_IRQ_WDOG (38) /* WDOG interrupt request out before wdg reset out */
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#define S32K1XX_IRQ_RCM (39) /* RCM Asynchronous Interrupt */
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#define S32K1XX_IRQ_LPI2C0 (40) /* LPI2C Master/Slave Interrupt */
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#define S32K1XX_IRQ_FLEXIO (41) /* FlexIO Interrupt */
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#define S32K1XX_IRQ_LPSPI0 (42) /* LPSPI0 Interrupt */
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#define S32K1XX_IRQ_LPSPI1 (43) /* LPSPI1 Interrupt */
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#define S32K1XX_IRQ_ADC0 (44) /* ADC0 Interrupt */
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#define S32K1XX_IRQ_CMP0 (45) /* CMP0 Interrupt */
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#define S32K1XX_IRQ_LPUART1 (46) /* LPUART1 Interrupt */
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#define S32K1XX_IRQ_LPUART1 (47) /* LPUART0 Interrupt */
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#define S32K_IRQ_NIRQS (48)
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#define S32K_IRQ_NEXTINT (S32K_IRQ_NIRQS - S32K_IRQ_FIRST)
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#define S32K1XX_IRQ_NIRQS (48)
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#define S32K1XX_IRQ_NEXTINT (S32K1XX_IRQ_NIRQS - S32K1XX_IRQ_INTERRUPT)
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/* Total number of IRQ numbers */
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#define NR_IRQS S32K_IRQ_NIRQS
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#define NR_IRQS S32K1XX_IRQ_NIRQS
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#endif /* __ARCH_ARM_INCLUDE_S32K1XX_S32K11XX_IRQ_H */
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@ -59,171 +59,171 @@
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/* Processor Exceptions (vectors 0-15) */
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#define S32K_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define S32K_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define S32K_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define S32K_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define S32K_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define S32K_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define S32K_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K_IRQ_SYSTICK (15) /* Vector 15: System tick */
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#define S32K1XX_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K1XX_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K1XX_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define S32K1XX_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define S32K1XX_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define S32K1XX_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define S32K1XX_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define S32K1XX_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define S32K1XX_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K1XX_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16). These definitions are chip-specific */
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#define S32K_IRQ_FIRST (16) /* Vector number of the first external interrupt */
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#define S32K1XX_IRQ_INTERRUPT (16) /* Vector number of the first external interrupt */
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#define S32K_IRQ_DMACH0 (16) /* DMA channel 0 transfer complete */
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#define S32K_IRQ_DMACH1 (17) /* DMA channel 1 transfer complete */
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#define S32K_IRQ_DMACH2 (18) /* DMA channel 2 transfer complete */
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#define S32K_IRQ_DMACH3 (19) /* DMA channel 3 transfer complete */
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#define S32K_IRQ_DMACH4 (20) /* DMA channel 4 transfer complete */
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#define S32K_IRQ_DMACH5 (21) /* DMA channel 5 transfer complete */
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#define S32K_IRQ_DMACH6 (22) /* DMA channel 6 transfer complete */
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#define S32K_IRQ_DMACH7 (23) /* DMA channel 7 transfer complete */
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#define S32K_IRQ_DMACH8 (24) /* DMA channel 8 transfer complete */
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#define S32K_IRQ_DMACH9 (25) /* DMA channel 9 transfer complete */
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#define S32K_IRQ_DMACH10 (26) /* DMA channel 10 transfer complete */
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#define S32K_IRQ_DMACH11 (27) /* DMA channel 11 transfer complete */
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#define S32K_IRQ_DMACH12 (28) /* DMA channel 12 transfer complete */
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#define S32K_IRQ_DMACH13 (29) /* DMA channel 13 transfer complete */
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#define S32K_IRQ_DMACH14 (30) /* DMA channel 14 transfer complete */
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#define S32K_IRQ_DMACH15 (31) /* DMA channel 15 transfer complete */
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#define S32K_IRQ_DMACH_ERR (32) /* DMA error interrupt channels 0-15 */
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#define S32K_IRQ_MCM (33) /* FPU sources */
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#define S32K_IRQ_FTFCCMD (34) /* FTFC command complete */
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#define S32K_IRQ_FTFCCOL (35) /* FTFC read collition */
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#define S32K_IRQ_PMC (36) /* PMC Low voltage detect interrupt */
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#define S32K_IRQ_FTFCDBL (37) /* FTFC Double bit */
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#define S32K_IRQ_WDOG (38) /* WDOG interrupt request out before wdg reset out */
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#define S32K_IRQ_EWM (38) /* EWM output as interrupt */
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#define S32K_IRQ_RCM (39) /* RCM Asynchronous Interrupt */
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#define S32K_IRQ_LPI2C0M (40) /* LPI2C Master Interrupt */
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#define S32K_IRQ_LPI2C0S (41) /* LPI2C Slave Interrupt */
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#define S32K_IRQ_LPSPI0 (42) /* LPSPI0 Interrupt */
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#define S32K_IRQ_LPSPI1 (43) /* LPSPI1 Interrupt */
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#define S32K_IRQ_LPSPI2 (44) /* LPSPI2 Interrupt */
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#define S32K_IRQ_LPI2C1M (45) /* LPI21 Master Interrupt */
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#define S32K_IRQ_LPI2C1S (46) /* LPI21 Slave Interrupt */
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#define S32K_IRQ_LPUART0 (47) /* LPUART0 Interrupt */
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/* Reserved (48) */
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#define S32K_IRQ_LPUART1 (49) /* LPUART1 Interrupt */
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/* Reserved (50) */
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#define S32K_IRQ_LPUART2 (51) /* LPUART0 Interrupt */
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/* Reserved (52-54) */
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#define S32K_IRQ_ADC0 (55) /* ADC0 Interrupt */
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#define S32K_IRQ_ADC1 (56) /* ADC1 Interrupt */
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#define S32K_IRQ_CMP0 (57) /* CMP0 Interrupt */
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/* Reserved (58-59) */
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#define S32K_IRQ_ERMS (60) /* ERM single bit error correction */
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#define S32K_IRQ_ERMD (61) /* ERM double bit error non-correctable */
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#define S32K_IRQ_RTC_ALARM (62) /* RTC alarm interrupt */
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#define S32K_IRQ_RTC_SEC (63) /* RTC seconds interrupt */
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#define S32K_IRQ_LPIT0 (64) /* LPIT interrupt */
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#define S32K_IRQ_LPIT1 (65) /* LPIT interrupt */
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#define S32K_IRQ_LPIT2 (66) /* LPIT interrupt */
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#define S32K_IRQ_LPIT3 (67) /* LPIT interrupt */
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#define S32K_IRQ_PDB0 (68) /* PDB0 interrupt */
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/* Reserved (69-70) */
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#define S32K_IRQ_SAI1TX (71) /* SAI1 Transmit Synchronous Interrupt */
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#define S32K_IRQ_SAI1RX (72) /* SAI1 Receive Synchronous Interrupt */
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#define S32K_IRQ_SCGBUS (73) /* SCG bus interrupt request */
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#define S32K_IRQ_LPTIMER (74) /* LPTIMER interrupt request */
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#define S32K_IRQ_PORTA (75) /* PORTA Interrupt */
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#define S32K_IRQ_PORTB (76) /* PORTB Interrupt */
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#define S32K_IRQ_PORTC (77) /* PORTC Interrupt */
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#define S32K_IRQ_PORTD (78) /* PORTD Interrupt */
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#define S32K_IRQ_PORTE (79) /* PORTE Interrupt */
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#define S32K_IRQ_SOFTWARE (80) /* Software Interrupt */
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#define S32K_IRQ_QUADSPI (81) /* QuadSPI Interrupts */
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/* Reserved (82-83) */
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#define S32K_IRQ_PDB1 (84) /* PDB1 Interrupt */
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#define S32K_IRQ_FLEXIO (85) /* FlexIO Interrupt */
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#define S32K_IRQ_SAI0_TX (86) /* SAI0 Transmit Synchronous Interrupt */
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#define S32K_IRQ_SAI0_RX (87) /* SAI0 Receive Synchronous Interrupt */
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#define S32K_IRQ_ENET_TIMER (88) /* ENET 1588 timer, time stamp, etc. */
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#define S32K_IRQ_ENET_TXDONE (89) /* ENET Data Tx Transfer Done Interrupt */
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#define S32K_IRQ_ENET_RXDONE (90) /* ENET Data Rx Transfer Done Interrupt */
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#define S32K_IRQ_ENET_ERROR (91) /* ENET Error Interrupt */
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#define S32K_IRQ_ENET_STOP (92) /* ENET Graceful Stop Interrupt */
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#define S32K_IRQ_ENET_WAKE (93) /* ENET Wake from Sleep Interrupt */
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#define S32K_IRQ_CAN0_BUS (94) /* CAN0 Bus On/Off Tx/Rx Warning */
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#define S32K_IRQ_CAN0_ERROR (95) /* CAN0 Bus Error Interrupt */
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#define S32K_IRQ_CAN0_LPRX (96) /* CAN0 Message Rx/Timeout in low power mode */
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#define S32K_IRQ_CAN0_0_15 (97) /* CAN0 OR'ed Message buffer (0-15) */
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#define S32K_IRQ_CAN0_16_31 (98) /* CAN0 OR'ed Message buffer (16-31) */
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/* Reserved (99-100) */
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#define S32K_IRQ_CAN1_BUS (101) /* CAN1 Bus On/Off Tx/Rx Warning */
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#define S32K_IRQ_CAN1_ERROR (102) /* CAN1 Bus Error Interrupt */
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/* Reserved (103) */
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#define S32K_IRQ_CAN1_0_15 (104) /* CAN1 OR'ed Message buffer (0-15) */
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#define S32K_IRQ_CAN1_16_31 (105) /* CAN1 OR'ed Message buffer (16-31) */
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/* Reserved (106-107) */
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#define S32K_IRQ_CAN2_BUS (108) /* CAN2 Bus On/Off Tx/Rx Warning */
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#define S32K_IRQ_CAN2_ERROR (109) /* CAN2 Bus Error Interrupt */
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/* Reserved (110) */
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#define S32K_IRQ_CAN2_0_15 (111) /* CAN2 OR'ed Message buffer (0-15) */
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#define S32K_IRQ_CAN2_16_31 (112) /* CAN2 OR'ed Message buffer (16-31) */
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/* Reserved (113-114) */
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#define S32K_IRQ_FTM0_CH0_1 (115) /* FTM0 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM0_CH2_2 (116) /* FTM0 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM0_CH4_5 (117) /* FTM0 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM0_CH6_7 (118) /* FTM0 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM0_FAULT (119) /* FTM0 Fault Interrupt */
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#define S32K_IRQ_FTM0_OVERFLOW (120) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM1_CH0_1 (121) /* FTM1 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM1_CH2_2 (122) /* FTM1 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM1_CH4_5 (123) /* FTM1 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM1_CH6_7 (124) /* FTM1 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM1_FAULT (125) /* FTM1 Fault Interrupt */
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#define S32K_IRQ_FTM1_OVERFLOW (126) /* FTM1 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM2_CH0_1 (127) /* FTM0 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM2_CH2_2 (128) /* FTM0 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM2_CH4_5 (129) /* FTM0 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM2_CH6_7 (130) /* FTM0 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM2_FAULT (131) /* FTM0 Fault Interrupt */
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#define S32K_IRQ_FTM2_OVERFLOW (132) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM3_CH0_1 (133) /* FTM3 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM3_CH2_2 (134) /* FTM3 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM3_CH4_5 (135) /* FTM3 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM3_CH6_7 (136) /* FTM3 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM3_FAULT (137) /* FTM3 Fault Interrupt */
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#define S32K_IRQ_FTM3_OVERFLOW (138) /* FTM3 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM4_CH0_1 (139) /* FTM4 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM4_CH2_2 (140) /* FTM4 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM4_CH4_5 (141) /* FTM4 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM4_CH6_7 (142) /* FTM4 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM4_FAULT (143) /* FTM4 Fault Interrupt */
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#define S32K_IRQ_FTM4_OVERFLOW (144) /* FTM4 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM5_CH0_1 (145) /* FTM5 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM5_CH2_2 (146) /* FTM5 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM5_CH4_5 (147) /* FTM5 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM5_CH6_7 (148) /* FTM5 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM5_FAULT (149) /* FTM5 Fault Interrupt */
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#define S32K_IRQ_FTM5_OVERFLOW (150) /* FTM5 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM6_CH0_1 (151) /* FTM6 Channel 0/1 Interrupt */
|
||||
#define S32K_IRQ_FTM6_CH2_2 (152) /* FTM6 Channel 2/3 Interrupt */
|
||||
#define S32K_IRQ_FTM6_CH4_5 (153) /* FTM6 Channel 4/5 Interrupt */
|
||||
#define S32K_IRQ_FTM6_CH6_7 (154) /* FTM6 Channel 6/7 Interrupt */
|
||||
#define S32K_IRQ_FTM6_FAULT (155) /* FTM6 Fault Interrupt */
|
||||
#define S32K_IRQ_FTM6_OVERFLOW (156) /* FTM6 Counter Overflow/Reload Interrupt */
|
||||
#define S32K_IRQ_FTM7_CH0_1 (157) /* FTM7 Channel 0/1 Interrupt */
|
||||
#define S32K_IRQ_FTM7_CH2_2 (158) /* FTM7 Channel 2/3 Interrupt */
|
||||
#define S32K_IRQ_FTM7_CH4_5 (159) /* FTM7 Channel 4/5 Interrupt */
|
||||
#define S32K_IRQ_FTM7_CH6_7 (160) /* FTM7 Channel 6/7 Interrupt */
|
||||
#define S32K_IRQ_FTM7_FAULT (161) /* FTM7 Fault Interrupt */
|
||||
#define S32K_IRQ_FTM7_OVERFLOW (162) /* FTM7 Counter Overflow/Reload Interrupt */
|
||||
#define S32K1XX_IRQ_DMACH0 (16) /* DMA channel 0 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH1 (17) /* DMA channel 1 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH2 (18) /* DMA channel 2 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH3 (19) /* DMA channel 3 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH4 (20) /* DMA channel 4 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH5 (21) /* DMA channel 5 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH6 (22) /* DMA channel 6 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH7 (23) /* DMA channel 7 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH8 (24) /* DMA channel 8 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH9 (25) /* DMA channel 9 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH10 (26) /* DMA channel 10 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH11 (27) /* DMA channel 11 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH12 (28) /* DMA channel 12 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH13 (29) /* DMA channel 13 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH14 (30) /* DMA channel 14 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH15 (31) /* DMA channel 15 transfer complete */
|
||||
#define S32K1XX_IRQ_DMACH_ERR (32) /* DMA error interrupt channels 0-15 */
|
||||
#define S32K1XX_IRQ_MCM (33) /* FPU sources */
|
||||
#define S32K1XX_IRQ_FTFCCMD (34) /* FTFC command complete */
|
||||
#define S32K1XX_IRQ_FTFCCOL (35) /* FTFC read collition */
|
||||
#define S32K1XX_IRQ_PMC (36) /* PMC Low voltage detect interrupt */
|
||||
#define S32K1XX_IRQ_FTFCDBL (37) /* FTFC Double bit */
|
||||
#define S32K1XX_IRQ_WDOG (38) /* WDOG interrupt request out before wdg reset out */
|
||||
#define S32K1XX_IRQ_EWM (38) /* EWM output as interrupt */
|
||||
#define S32K1XX_IRQ_RCM (39) /* RCM Asynchronous Interrupt */
|
||||
#define S32K1XX_IRQ_LPI2C0M (40) /* LPI2C Master Interrupt */
|
||||
#define S32K1XX_IRQ_LPI2C0S (41) /* LPI2C Slave Interrupt */
|
||||
#define S32K1XX_IRQ_LPSPI0 (42) /* LPSPI0 Interrupt */
|
||||
#define S32K1XX_IRQ_LPSPI1 (43) /* LPSPI1 Interrupt */
|
||||
#define S32K1XX_IRQ_LPSPI2 (44) /* LPSPI2 Interrupt */
|
||||
#define S32K1XX_IRQ_LPI2C1M (45) /* LPI21 Master Interrupt */
|
||||
#define S32K1XX_IRQ_LPI2C1S (46) /* LPI21 Slave Interrupt */
|
||||
#define S32K1XX_IRQ_LPUART0 (47) /* LPUART0 Interrupt */
|
||||
/* Reserved (48) */
|
||||
#define S32K1XX_IRQ_LPUART1 (49) /* LPUART1 Interrupt */
|
||||
/* Reserved (50) */
|
||||
#define S32K1XX_IRQ_LPUART2 (51) /* LPUART0 Interrupt */
|
||||
/* Reserved (52-54) */
|
||||
#define S32K1XX_IRQ_ADC0 (55) /* ADC0 Interrupt */
|
||||
#define S32K1XX_IRQ_ADC1 (56) /* ADC1 Interrupt */
|
||||
#define S32K1XX_IRQ_CMP0 (57) /* CMP0 Interrupt */
|
||||
/* Reserved (58-59) */
|
||||
#define S32K1XX_IRQ_ERMS (60) /* ERM single bit error correction */
|
||||
#define S32K1XX_IRQ_ERMD (61) /* ERM double bit error non-correctable */
|
||||
#define S32K1XX_IRQ_RTC_ALARM (62) /* RTC alarm interrupt */
|
||||
#define S32K1XX_IRQ_RTC_SEC (63) /* RTC seconds interrupt */
|
||||
#define S32K1XX_IRQ_LPIT0 (64) /* LPIT interrupt */
|
||||
#define S32K1XX_IRQ_LPIT1 (65) /* LPIT interrupt */
|
||||
#define S32K1XX_IRQ_LPIT2 (66) /* LPIT interrupt */
|
||||
#define S32K1XX_IRQ_LPIT3 (67) /* LPIT interrupt */
|
||||
#define S32K1XX_IRQ_PDB0 (68) /* PDB0 interrupt */
|
||||
/* Reserved (69-70) */
|
||||
#define S32K1XX_IRQ_SAI1TX (71) /* SAI1 Transmit Synchronous Interrupt */
|
||||
#define S32K1XX_IRQ_SAI1RX (72) /* SAI1 Receive Synchronous Interrupt */
|
||||
#define S32K1XX_IRQ_SCGBUS (73) /* SCG bus interrupt request */
|
||||
#define S32K1XX_IRQ_LPTIMER (74) /* LPTIMER interrupt request */
|
||||
#define S32K1XX_IRQ_PORTA (75) /* PORTA Interrupt */
|
||||
#define S32K1XX_IRQ_PORTB (76) /* PORTB Interrupt */
|
||||
#define S32K1XX_IRQ_PORTC (77) /* PORTC Interrupt */
|
||||
#define S32K1XX_IRQ_PORTD (78) /* PORTD Interrupt */
|
||||
#define S32K1XX_IRQ_PORTE (79) /* PORTE Interrupt */
|
||||
#define S32K1XX_IRQ_SOFTWARE (80) /* Software Interrupt */
|
||||
#define S32K1XX_IRQ_QUADSPI (81) /* QuadSPI Interrupts */
|
||||
/* Reserved (82-83) */
|
||||
#define S32K1XX_IRQ_PDB1 (84) /* PDB1 Interrupt */
|
||||
#define S32K1XX_IRQ_FLEXIO (85) /* FlexIO Interrupt */
|
||||
#define S32K1XX_IRQ_SAI0_TX (86) /* SAI0 Transmit Synchronous Interrupt */
|
||||
#define S32K1XX_IRQ_SAI0_RX (87) /* SAI0 Receive Synchronous Interrupt */
|
||||
#define S32K1XX_IRQ_ENET_TIMER (88) /* ENET 1588 timer, time stamp, etc. */
|
||||
#define S32K1XX_IRQ_ENET_TXDONE (89) /* ENET Data Tx Transfer Done Interrupt */
|
||||
#define S32K1XX_IRQ_ENET_RXDONE (90) /* ENET Data Rx Transfer Done Interrupt */
|
||||
#define S32K1XX_IRQ_ENET_ERROR (91) /* ENET Error Interrupt */
|
||||
#define S32K1XX_IRQ_ENET_STOP (92) /* ENET Graceful Stop Interrupt */
|
||||
#define S32K1XX_IRQ_ENET_WAKE (93) /* ENET Wake from Sleep Interrupt */
|
||||
#define S32K1XX_IRQ_CAN0_BUS (94) /* CAN0 Bus On/Off Tx/Rx Warning */
|
||||
#define S32K1XX_IRQ_CAN0_ERROR (95) /* CAN0 Bus Error Interrupt */
|
||||
#define S32K1XX_IRQ_CAN0_LPRX (96) /* CAN0 Message Rx/Timeout in low power mode */
|
||||
#define S32K1XX_IRQ_CAN0_0_15 (97) /* CAN0 OR'ed Message buffer (0-15) */
|
||||
#define S32K1XX_IRQ_CAN0_16_31 (98) /* CAN0 OR'ed Message buffer (16-31) */
|
||||
/* Reserved (99-100) */
|
||||
#define S32K1XX_IRQ_CAN1_BUS (101) /* CAN1 Bus On/Off Tx/Rx Warning */
|
||||
#define S32K1XX_IRQ_CAN1_ERROR (102) /* CAN1 Bus Error Interrupt */
|
||||
/* Reserved (103) */
|
||||
#define S32K1XX_IRQ_CAN1_0_15 (104) /* CAN1 OR'ed Message buffer (0-15) */
|
||||
#define S32K1XX_IRQ_CAN1_16_31 (105) /* CAN1 OR'ed Message buffer (16-31) */
|
||||
/* Reserved (106-107) */
|
||||
#define S32K1XX_IRQ_CAN2_BUS (108) /* CAN2 Bus On/Off Tx/Rx Warning */
|
||||
#define S32K1XX_IRQ_CAN2_ERROR (109) /* CAN2 Bus Error Interrupt */
|
||||
/* Reserved (110) */
|
||||
#define S32K1XX_IRQ_CAN2_0_15 (111) /* CAN2 OR'ed Message buffer (0-15) */
|
||||
#define S32K1XX_IRQ_CAN2_16_31 (112) /* CAN2 OR'ed Message buffer (16-31) */
|
||||
/* Reserved (113-114) */
|
||||
#define S32K1XX_IRQ_FTM0_CH0_1 (115) /* FTM0 Channel 0/1 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM0_CH2_2 (116) /* FTM0 Channel 2/3 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM0_CH4_5 (117) /* FTM0 Channel 4/5 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM0_CH6_7 (118) /* FTM0 Channel 6/7 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM0_FAULT (119) /* FTM0 Fault Interrupt */
|
||||
#define S32K1XX_IRQ_FTM0_OVERFLOW (120) /* FTM0 Counter Overflow/Reload Interrupt */
|
||||
#define S32K1XX_IRQ_FTM1_CH0_1 (121) /* FTM1 Channel 0/1 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM1_CH2_2 (122) /* FTM1 Channel 2/3 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM1_CH4_5 (123) /* FTM1 Channel 4/5 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM1_CH6_7 (124) /* FTM1 Channel 6/7 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM1_FAULT (125) /* FTM1 Fault Interrupt */
|
||||
#define S32K1XX_IRQ_FTM1_OVERFLOW (126) /* FTM1 Counter Overflow/Reload Interrupt */
|
||||
#define S32K1XX_IRQ_FTM2_CH0_1 (127) /* FTM0 Channel 0/1 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM2_CH2_2 (128) /* FTM0 Channel 2/3 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM2_CH4_5 (129) /* FTM0 Channel 4/5 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM2_CH6_7 (130) /* FTM0 Channel 6/7 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM2_FAULT (131) /* FTM0 Fault Interrupt */
|
||||
#define S32K1XX_IRQ_FTM2_OVERFLOW (132) /* FTM0 Counter Overflow/Reload Interrupt */
|
||||
#define S32K1XX_IRQ_FTM3_CH0_1 (133) /* FTM3 Channel 0/1 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM3_CH2_2 (134) /* FTM3 Channel 2/3 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM3_CH4_5 (135) /* FTM3 Channel 4/5 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM3_CH6_7 (136) /* FTM3 Channel 6/7 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM3_FAULT (137) /* FTM3 Fault Interrupt */
|
||||
#define S32K1XX_IRQ_FTM3_OVERFLOW (138) /* FTM3 Counter Overflow/Reload Interrupt */
|
||||
#define S32K1XX_IRQ_FTM4_CH0_1 (139) /* FTM4 Channel 0/1 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM4_CH2_2 (140) /* FTM4 Channel 2/3 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM4_CH4_5 (141) /* FTM4 Channel 4/5 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM4_CH6_7 (142) /* FTM4 Channel 6/7 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM4_FAULT (143) /* FTM4 Fault Interrupt */
|
||||
#define S32K1XX_IRQ_FTM4_OVERFLOW (144) /* FTM4 Counter Overflow/Reload Interrupt */
|
||||
#define S32K1XX_IRQ_FTM5_CH0_1 (145) /* FTM5 Channel 0/1 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM5_CH2_2 (146) /* FTM5 Channel 2/3 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM5_CH4_5 (147) /* FTM5 Channel 4/5 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM5_CH6_7 (148) /* FTM5 Channel 6/7 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM5_FAULT (149) /* FTM5 Fault Interrupt */
|
||||
#define S32K1XX_IRQ_FTM5_OVERFLOW (150) /* FTM5 Counter Overflow/Reload Interrupt */
|
||||
#define S32K1XX_IRQ_FTM6_CH0_1 (151) /* FTM6 Channel 0/1 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM6_CH2_2 (152) /* FTM6 Channel 2/3 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM6_CH4_5 (153) /* FTM6 Channel 4/5 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM6_CH6_7 (154) /* FTM6 Channel 6/7 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM6_FAULT (155) /* FTM6 Fault Interrupt */
|
||||
#define S32K1XX_IRQ_FTM6_OVERFLOW (156) /* FTM6 Counter Overflow/Reload Interrupt */
|
||||
#define S32K1XX_IRQ_FTM7_CH0_1 (157) /* FTM7 Channel 0/1 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM7_CH2_2 (158) /* FTM7 Channel 2/3 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM7_CH4_5 (159) /* FTM7 Channel 4/5 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM7_CH6_7 (160) /* FTM7 Channel 6/7 Interrupt */
|
||||
#define S32K1XX_IRQ_FTM7_FAULT (161) /* FTM7 Fault Interrupt */
|
||||
#define S32K1XX_IRQ_FTM7_OVERFLOW (162) /* FTM7 Counter Overflow/Reload Interrupt */
|
||||
|
||||
#define S32K_IRQ_NIRQS (163)
|
||||
#define S32K_IRQ_NEXTINT (S32K_IRQ_NIRQS - S32K_IRQ_FIRST)
|
||||
#define S32K1XX_IRQ_NIRQS (163)
|
||||
#define S32K1XX_IRQ_NEXTINT (S32K1XX_IRQ_NIRQS - S32K1XX_IRQ_INTERRUPT)
|
||||
|
||||
/* Total number of IRQ numbers */
|
||||
|
||||
#define NR_IRQS S32K_IRQ_NIRQS
|
||||
#define NR_IRQS S32K1XX_IRQ_NIRQS
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_S32K1XX_S32K14XX_IRQ_H */
|
||||
|
||||
|
||||
@ -52,7 +52,7 @@ endif
|
||||
# Source files common to all S32K1xx chip families.
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = s32k1xx_start.c
|
||||
CHIP_CSRCS = s32k1xx_start.c s32k1xx_clockconfig.c
|
||||
|
||||
# Source files specific to the ARM CPU family and to the S32K1xx chip family
|
||||
|
||||
|
||||
@ -55,8 +55,8 @@
|
||||
* arch/s32k1xx/irq.h header file.
|
||||
*/
|
||||
|
||||
#define ARMV6M_PERIPHERAL_INTERRUPTS S32K_IRQ_NEXTINT
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS S32K_IRQ_NEXTINT
|
||||
#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -35,12 +35,10 @@
|
||||
|
||||
# Source files specific to the Cortex-M0+
|
||||
|
||||
HEAD_ASRC =
|
||||
|
||||
CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S
|
||||
CMN_ASRCS += up_exception.S up_saveusercontext.S up_fullcontextrestore.S
|
||||
CMN_ASRCS += up_switchcontext.S vfork.S
|
||||
|
||||
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
|
||||
CMN_CSRCS += up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
|
||||
CMN_CSRCS += up_initialstate.c up_releasepending.c up_reprioritizertr.c
|
||||
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_systemreset.c
|
||||
CMN_CSRCS += up_unblocktask.c up_doirq.c up_hardfault.c up_svcall.c
|
||||
@ -57,8 +55,7 @@ endif
|
||||
|
||||
# Source file specific to the S32k11x family
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = s32k11x_irq.c
|
||||
CHIP_CSRCS += s32k11x_irq.c
|
||||
|
||||
# Configuration-dependent S32k11x files
|
||||
|
||||
|
||||
@ -50,7 +50,7 @@
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "s32k14x/s32k14x_irq.h"
|
||||
#include "s32k11x/s32k11x_irq.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -137,7 +137,8 @@ static inline void s32k11x_clrpend(int irq)
|
||||
|
||||
/* Check for an external interrupt */
|
||||
|
||||
if (irq >= S32K1XX_IRQ_INTERRUPT && irq < S32K1XX_IRQ_INTERRUPT + S32K1XX_IRQ_NINTS)
|
||||
if (irq >= S32K1XX_IRQ_INTERRUPT &&
|
||||
irq < S32K1XX_IRQ_INTERRUPT + S32K1XX_IRQ_NEXTINT)
|
||||
{
|
||||
/* Set the appropriate bit in the ISER register to enable the
|
||||
* interrupt
|
||||
@ -222,7 +223,8 @@ void up_disable_irq(int irq)
|
||||
|
||||
/* Check for an external interrupt */
|
||||
|
||||
if (irq >= S32K1XX_IRQ_INTERRUPT && irq < S32K1XX_IRQ_INTERRUPT + S32K1XX_IRQ_NINTS)
|
||||
if (irq >= S32K1XX_IRQ_INTERRUPT &&
|
||||
irq < S32K1XX_IRQ_INTERRUPT + S32K1XX_IRQ_NEXTINT)
|
||||
{
|
||||
/* Set the appropriate bit in the ICER register to disable the
|
||||
* interrupt
|
||||
@ -259,7 +261,8 @@ void up_enable_irq(int irq)
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= S32K1XX_IRQ_INTERRUPT && irq < S32K1XX_IRQ_INTERRUPT + S32K1XX_IRQ_NINTS)
|
||||
if (irq >= S32K1XX_IRQ_INTERRUPT &&
|
||||
irq < S32K1XX_IRQ_INTERRUPT + S32K1XX_IRQ_NEXTINT)
|
||||
{
|
||||
/* Set the appropriate bit in the ISER register to enable the
|
||||
* interrupt
|
||||
|
||||
@ -41,14 +41,17 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "clock/clock.h"
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "clock/clock.h"
|
||||
#include "s32k1xx_clockconfig.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -59,9 +62,13 @@
|
||||
* system clock ticks per second. That value is a user configurable setting
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*
|
||||
* Then, for example, if the CPU clock is the SysTick and
|
||||
* BOARD_CPU_FREQUENCY is 48MHz and CLK_TCK is 100, then the reload value
|
||||
* would be:
|
||||
* The CLKSOURCE field in SysTick Control and Status register selects either
|
||||
* the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock
|
||||
* (when CLKSOURCE = 0).
|
||||
|
||||
* Then, for example, if the core clock is the SysTick close source and
|
||||
* the core clock is 48MHz and CLK_TCK is 100, then the reload value would
|
||||
* be:
|
||||
*
|
||||
* SYSTICK_RELOAD = (48,000,000 / 100) - 1
|
||||
* = 479,999
|
||||
@ -70,15 +77,7 @@
|
||||
* Which fits within the maximum 24-bit reload value.
|
||||
*/
|
||||
|
||||
#define SYSTICK_RELOAD ((BOARD_CPU_FREQUENCY / CLK_TCK) - 1)
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify that the reload value
|
||||
* will fit in the reload register.
|
||||
*/
|
||||
|
||||
#if SYSTICK_RELOAD > 0x00ffffff
|
||||
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
|
||||
#endif
|
||||
#define SYSTICK_RELOAD(coreclk) (((coreclk) / CLK_TCK) - 1)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
@ -116,18 +115,35 @@ static int s32k11x_timerisr(int irq, uint32_t *regs, void *arg)
|
||||
|
||||
void arm_timer_initialize(void)
|
||||
{
|
||||
uint32_t coreclk;
|
||||
uint32_t reload;
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the SysTick interrupt to the default priority */
|
||||
|
||||
regval = getreg32(ARMV6M_SYSCON_SHPR3);
|
||||
regval = getreg32(ARMV6M_SYSCON_SHPR3);
|
||||
regval &= ~SYSCON_SHPR3_PRI_15_MASK;
|
||||
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT);
|
||||
putreg32(regval, ARMV6M_SYSCON_SHPR3);
|
||||
|
||||
/* Set set CSR CLKSOURCE bit to select the core clock as the SysTick
|
||||
* source clock.
|
||||
*/
|
||||
|
||||
putreg32(SYSTICK_CSR_CLKSOURCE, ARMV6M_SYSTICK_CSR);
|
||||
|
||||
/* Get the reload value */
|
||||
|
||||
coreclk = s32k1xx_get_coreclk();
|
||||
reload = SYSTICK_RELOAD(coreclk);
|
||||
|
||||
/* The size of the reload field is 24 bits. */
|
||||
|
||||
DEBUGASSERT(reload <= 0x00ffffff);
|
||||
|
||||
/* Configure SysTick to interrupt at the requested rate */
|
||||
|
||||
putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR);
|
||||
putreg32(reload, ARMV6M_SYSTICK_RVR);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
@ -135,7 +151,8 @@ void arm_timer_initialize(void)
|
||||
|
||||
/* Enable SysTick interrupts */
|
||||
|
||||
putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR);
|
||||
putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE |SYSTICK_CSR_CLKSOURCE),
|
||||
ARMV6M_SYSTICK_CSR);
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
|
||||
@ -41,30 +41,27 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "clock/clock.h"
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "hardware/s32k14x_syscon.h"
|
||||
#include "clock/clock.h"
|
||||
#include "s32k1xx_clockconfig.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* The SysTick clock may be clocked internally either by the by the system
|
||||
* clock (CLKSOURCE==1) or by the SysTick function clock (CLKSOURCE==0).
|
||||
* The SysTick Function clock is equal to:
|
||||
*
|
||||
* Fsystick = Fmainclk / SYSTICKCLKDIV
|
||||
*
|
||||
* Both the divider value (BOARD_SYSTICKCLKDIV) and the resulting SysTick
|
||||
* function clock frequency (Fsystick, BOARD_SYSTICK_CLOCK)
|
||||
/* The SysTick clock input (Fsystick) is determined by the CLKSOURCE file of
|
||||
* the SysTick CSR register: The CLKSOURCE field in SysTick Control and
|
||||
* Status register selects either the core clock (when CLKSOURCE = 1) or a
|
||||
* divide-by-16 of the core clock (when CLKSOURCE = 0).
|
||||
*
|
||||
* The desired timer interrupt frequency is provided by the definition
|
||||
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
|
||||
@ -72,22 +69,9 @@
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*
|
||||
* reload = (Fsystick / CLK_TICK) - 1
|
||||
*
|
||||
* Tips for selecting BOARD_SYSTICKCLKDIV: The resulting reload value
|
||||
* should be as large as possible, but must be less than 2^24:
|
||||
*
|
||||
* SYSTICKDIV > Fmainclk / CLK_TCK / 2^24
|
||||
*/
|
||||
|
||||
#define SYSTICK_RELOAD ((BOARD_SYSTICK_CLOCK / CLK_TCK) - 1)
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify that the reload value
|
||||
* will fit in the reload register.
|
||||
*/
|
||||
|
||||
#if SYSTICK_RELOAD > 0x00ffffff
|
||||
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
|
||||
#endif
|
||||
#define SYSTICK_RELOAD(coreclk) (((coreclk) / CLK_TCK) - 1)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
@ -125,38 +109,28 @@ static int s32k14x_timerisr(int irq, uint32_t *regs, void *arg)
|
||||
|
||||
void arm_timer_initialize(void)
|
||||
{
|
||||
uint32_t coreclk;
|
||||
uint32_t reload;
|
||||
uint32_t regval;
|
||||
|
||||
/* May be clocked internally by the system clock or the SysTick function
|
||||
* clock. Set the SysTick clock divider in the SYSCON_SYSTICK register.
|
||||
* Since this function is called early after reset, it is safe to assume
|
||||
* that the SysTick is disabled and so that no reset or halt actions are
|
||||
* necessary.
|
||||
*/
|
||||
|
||||
regval = (SYSCON_SYSTICKCLKDIV_DIV(BOARD_SYSTICKCLKDIV) |
|
||||
SYSCON_SYSTICKCLKDIV_REQFLAG);
|
||||
putreg32(regval, S32K1XX_SYSCON_SYSTICKCLKDIV);
|
||||
|
||||
/* The request flag will be cleared when the divider change is complete */
|
||||
|
||||
while ((getreg32(S32K1XX_SYSCON_SYSTICKCLKDIV) & SYSCON_SYSTICKCLKDIV_REQFLAG) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Make sure that the SYSTICK clock source is set to use the SysTick
|
||||
* function clock (CLKSOURCE==0).
|
||||
*
|
||||
* REVISIT: This is over-writted with CLKSOURCE==1 below.
|
||||
* function clock (CLKSOURCE==1).
|
||||
*/
|
||||
|
||||
regval = getreg32(NVIC_SYSTICK_CTRL);
|
||||
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
|
||||
putreg32(regval, NVIC_SYSTICK_CTRL);
|
||||
putreg32(NVIC_SYSTICK_CTRL_CLKSOURCE, NVIC_SYSTICK_CTRL);
|
||||
|
||||
/* Get the reload value */
|
||||
|
||||
coreclk = s32k1xx_get_coreclk();
|
||||
reload = SYSTICK_RELOAD(coreclk);
|
||||
|
||||
/* The size of the reload field is 24 bits. */
|
||||
|
||||
DEBUGASSERT(reload <= 0x00ffffff);
|
||||
|
||||
/* Configure SysTick to interrupt at the requested rate */
|
||||
|
||||
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
|
||||
putreg32(reload, NVIC_SYSTICK_RELOAD);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
|
||||
75
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
Normal file
75
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
Normal file
@ -0,0 +1,75 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "s32k1xx_clockconfig.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: s32k1xx_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the S32K1XX. This does whatever setup is needed
|
||||
* to put the MCU in a usable state. This includes the initialization of
|
||||
* clocking using the settings in board.h. This function also performs
|
||||
* other low-level chip as necessary.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
void s32k1xx_clockconfig(FAR const struct pll_setup_s *pllsetup)
|
||||
{
|
||||
#warning Missing logic
|
||||
}
|
||||
126
arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
Normal file
126
arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
Normal file
@ -0,0 +1,126 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_CLKCONFIG_H
|
||||
#define __ARCH_ARM_SRC_S32K1XX_S32K1XX_CLKCONFIG_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/* PLL setup structure.
|
||||
*
|
||||
* This structure can be used to define a PLL configuration. If powering
|
||||
* up or waiting for PLL lock, the PLL input clock source should be
|
||||
* configured prior to PLL setup.
|
||||
*/
|
||||
|
||||
struct pll_setup_s
|
||||
{
|
||||
uint32_t pllclksel; /* PLL clock source register SYSPLLCLKSEL */
|
||||
uint32_t pllctrl; /* PLL control register SYSPLLCTRL */
|
||||
uint32_t pllndec; /* PLL NDEC register SYSPLLNDEC */
|
||||
uint32_t pllpdec; /* PLL PDEC register SYSPLLPDEC */
|
||||
uint32_t pllmdec; /* PLL MDEC registers SYSPLLPDEC */
|
||||
uint32_t pllfout; /* Actual PLL output frequency */
|
||||
uint32_t pllfrac; /* Only aduio PLL has this function*/
|
||||
uint32_t pllflags; /* PLL setup flags */
|
||||
uint32_t ahbdiv; /* AHB divider */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: s32k1xx_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the S32K1XX. This does whatever setup is needed
|
||||
* to put the MCU in a usable state. This includes the initialization of
|
||||
* clocking using the settings in board.h. This function also performs
|
||||
* other low-level chip as necessary.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
void s32k1xx_clockconfig(FAR const struct pll_setup_s *pllsetup);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: s32k1xx_get_coreclk
|
||||
*
|
||||
* Description:
|
||||
* Return the current selection of the CORE clock.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
uint32_t s32k1xx_get_coreclk(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_CLKCONFIG_H */
|
||||
271
arch/arm/src/s32k1xx/s32k1xx_start.c
Normal file
271
arch/arm/src/s32k1xx/s32k1xx_start.c
Normal file
@ -0,0 +1,271 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/x32k1xx/s32k1xx_start.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/init.h>
|
||||
#include <arch/board/board.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "nvic.h"
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
# include "s32k1xx_userspace.h"
|
||||
#endif
|
||||
|
||||
#include "s32k1xx_clockconfig.h"
|
||||
#include "s32k1xx_lowputc.h"
|
||||
#include "s32k1xx_serial.h"
|
||||
#include "s32k1xx_start.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: showprogress
|
||||
*
|
||||
* Description:
|
||||
* Print a character on the UART to show boot status.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
# define showprogress(c) up_lowputc(c)
|
||||
#else
|
||||
# define showprogress(c)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This describes the initial PLL configuration */
|
||||
|
||||
static const struct pll_setup_s g_initial_pll_setup =
|
||||
{
|
||||
0 /* REVISIT */
|
||||
#warning Missing logic
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: s32k1xx_fpuconfig
|
||||
*
|
||||
* Description:
|
||||
* Configure the FPU. Relative bit settings:
|
||||
*
|
||||
* CPACR: Enables access to CP10 and CP11
|
||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
||||
* current context:
|
||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
||||
* processor sets this bit to 1 on successful completion of any FP
|
||||
* instruction.
|
||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
||||
* done, the processor reserves space on the stack for the FP state,
|
||||
* but does not save that state information to the stack.
|
||||
*
|
||||
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
|
||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
||||
* extension, or
|
||||
* - the CONTROL.FPCA bit is set to 1
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
||||
static inline void s32k1xx_fpuconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
||||
* with the volatile FP registers stacked above the basic context.
|
||||
*/
|
||||
|
||||
regval = getcontrol();
|
||||
regval |= (1 << 2);
|
||||
setcontrol(regval);
|
||||
|
||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
||||
* are going to turn on CONTROL.FPCA for all contexts.
|
||||
*/
|
||||
|
||||
regval = getreg32(NVIC_FPCCR);
|
||||
regval &= ~((1 << 31) | (1 << 30));
|
||||
putreg32(regval, NVIC_FPCCR);
|
||||
|
||||
/* Enable full access to CP10 and CP11 */
|
||||
|
||||
regval = getreg32(NVIC_CPACR);
|
||||
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
|
||||
putreg32(regval, NVIC_CPACR);
|
||||
}
|
||||
#else
|
||||
static inline void s32k1xx_fpuconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
||||
* with the volatile FP registers stacked in the saved context.
|
||||
*/
|
||||
|
||||
regval = getcontrol();
|
||||
regval &= ~(1 << 2);
|
||||
setcontrol(regval);
|
||||
|
||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
||||
* are going to keep CONTROL.FPCA off for all contexts.
|
||||
*/
|
||||
|
||||
regval = getreg32(NVIC_FPCCR);
|
||||
regval &= ~((1 << 31) | (1 << 30));
|
||||
putreg32(regval, NVIC_FPCCR);
|
||||
|
||||
/* Enable full access to CP10 and CP11 */
|
||||
|
||||
regval = getreg32(NVIC_CPACR);
|
||||
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
|
||||
putreg32(regval, NVIC_CPACR);
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
# define s32k1xx_fpuconfig()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: _start
|
||||
*
|
||||
* Description:
|
||||
* This is the reset entry point.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
const uint32_t *src;
|
||||
uint32_t *dest;
|
||||
uint32_t regval;
|
||||
|
||||
/* Make sure that interrupts are disabled */
|
||||
|
||||
__asm__ __volatile__ ("\tcpsid i\n");
|
||||
|
||||
/* Configure the clocking and the console uart so that we can get debug
|
||||
* output as soon as possible. NOTE: That this logic must not assume that
|
||||
* .bss or .data have beeninitialized.
|
||||
*/
|
||||
|
||||
s32k1xx_clockconfig(&g_initial_pll_setup);
|
||||
s32k1xx_lowsetup();
|
||||
showprogress('A');
|
||||
|
||||
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
|
||||
* certain that there are no issues with the state of global variables.
|
||||
*/
|
||||
|
||||
for (dest = &_sbss; dest < &_ebss; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
showprogress('B');
|
||||
|
||||
/* Move the initialized data section from his temporary holding spot in
|
||||
* FLASH into the correct place in SRAM. The correct place in SRAM is
|
||||
* give by _sdata and _edata. The temporary location is in FLASH at the
|
||||
* end of all of the other read-only data (.text, .rodata) at _eronly.
|
||||
*/
|
||||
|
||||
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
showprogress('C');
|
||||
|
||||
/* Initialize the FPU (if configured) */
|
||||
|
||||
s32k1xx_fpuconfig();
|
||||
showprogress('D');
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
s32k1xx_earlyserialinit();
|
||||
#endif
|
||||
showprogress('E');
|
||||
|
||||
/* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
s32k1xx_userspace();
|
||||
showprogress('F');
|
||||
#endif
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
s32k1xx_board_initialize();
|
||||
showprogress('G');
|
||||
|
||||
/* Then start NuttX */
|
||||
|
||||
showprogress('\r');
|
||||
showprogress('\n');
|
||||
nx_start();
|
||||
|
||||
/* Shouldn't get here */
|
||||
|
||||
for (; ; );
|
||||
}
|
||||
88
arch/arm/src/s32k1xx/s32k1xx_start.h
Normal file
88
arch/arm/src/s32k1xx/s32k1xx_start.h
Normal file
@ -0,0 +1,88 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/s32k1xx/s32k1xx_start.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_START_H
|
||||
#define __ARCH_ARM_SRC_S32K1XX_S32K1XX_START_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
|
||||
* script. _ebss lies at the end of the BSS region. The idle task stack starts at
|
||||
* the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
|
||||
* the thread that the system boots on and, eventually, becomes the IDLE, do
|
||||
* nothing task that runs only when there is nothing else to run. The heap
|
||||
* continues from there until the end of memory. g_idle_topstack is a read-only
|
||||
* variable the provides this computed address.
|
||||
*/
|
||||
|
||||
extern const uintptr_t g_idle_topstack;
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: s32k1xx_board_initialize
|
||||
*
|
||||
* Description:
|
||||
* All S32K1XX architectures must provide the following entry point. This entry
|
||||
* point is called early in the initialization -- after clocking and memory have
|
||||
* been configured but before caches have been enabled and before any devices have
|
||||
* been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void s32k1xx_board_initialize(void);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_START_H */
|
||||
@ -50,7 +50,7 @@
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: s32k118_boardinitialize
|
||||
* Name: s32k1xx_board_initialize
|
||||
*
|
||||
* Description:
|
||||
* All S32K1XX architectures must provide the following entry point. This
|
||||
@ -60,7 +60,7 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void s32k118_boardinitialize(void)
|
||||
void s32k1xx_board_initialize(void)
|
||||
{
|
||||
#ifdef CONFIG_S32K1XX_SPI
|
||||
/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak
|
||||
|
||||
Loading…
Reference in New Issue
Block a user