NXP RDDRONE-UAVCAN boards (S32K1XX) - Clean up clock config (#557)
* RDDRONE-UAVCAN boards - Clean up clock config * S32K1XX - Style fix 3
This commit is contained in:
Jari van Ewijk
GitHub
parent
850c7faaa8
commit
963ee6f42e
@ -86,7 +86,7 @@
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/* Count of peripheral clock user configurations */
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#define NUM_OF_PERIPHERAL_CLOCKS_0 15
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#define NUM_OF_PERIPHERAL_CLOCKS_0 11
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/****************************************************************************
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* Public Types
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@ -77,151 +77,141 @@ const struct clock_configuration_s g_initial_clkconfig =
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{
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.scg =
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{
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.sirc =
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.sirc =
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{
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.range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
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.initialize = true, /* Initialize */
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.stopmode = true, /* SIRCSTEN */
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.lowpower = true, /* SIRCLPEN */
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.locked = false, /* LK */
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.range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
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.initialize = true, /* Initialize */
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.stopmode = false, /* SIRCSTEN */
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.lowpower = true, /* SIRCLPEN */
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.locked = false, /* LK */
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},
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.firc =
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.firc =
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{
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.range = SCG_FIRC_RANGE_48M, /* RANGE */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
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.initialize = true, /* Initialize */
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.stopmode = false, /* */
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.lowpower = false, /* */
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.regulator = true, /* FIRCREGOFF */
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.locked = false, /* LK */
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.range = SCG_FIRC_RANGE_48M, /* RANGE */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
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.initialize = true, /* Initialize */
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.regulator = true, /* FIRCREGOFF */
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.locked = false, /* LK */
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},
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.sosc =
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.sosc =
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{
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.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
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.gain = SCG_SOSC_GAIN_LOW, /* HGO */
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.range = SCG_SOSC_RANGE_MID, /* RANGE */
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.extref = SCG_SOSC_REF_OSC, /* EREFS */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
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.initialize = true, /* Initialize */
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.stopmode = false, /* */
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.lowpower = false, /* */
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.locked = false, /* LK */
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.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
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.gain = SCG_SOSC_GAIN_LOW, /* HGO */
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.range = SCG_SOSC_RANGE_HIGH, /* RANGE */
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.extref = SCG_SOSC_REF_OSC, /* EREFS */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
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.initialize = true, /* Initialize */
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.locked = false, /* LK */
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},
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.spll =
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.spll =
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{
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.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
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.prediv = 1, /* PREDIV */
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.mult = 40, /* MULT */
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.src = 0, /* SOURCE */
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.initialize = true, /* Initialize */
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.stopmode = false, /* */
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.locked = false, /* LK */
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.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
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.prediv = 1, /* PREDIV */
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.mult = 40, /* MULT */
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.src = 0, /* SOURCE */
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.initialize = true, /* Initialize */
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.locked = false, /* LK */
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},
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.rtc =
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.rtc =
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{
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.initialize = true, /* Initialize */
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.clkin = 0 /* RTC_CLKIN */
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.initialize = true, /* Initialize */
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.clkin = 0, /* RTC_CLKIN */
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},
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.clockout =
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.clockout =
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{
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.source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
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.initialize = true, /* Initialize */
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.source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
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.initialize = true, /* Initialize */
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},
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.clockmode =
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.clockmode =
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{
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.rccr = /* RCCR - Run Clock Control Register */
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.rccr = /* RCCR - Run Clock Control Register */
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2 /* DIVCORE, range 1..16 */
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2, /* DIVCORE, range 1..16 */
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},
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.vccr = /* VCCR - VLPR Clock Control Register */
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.vccr = /* VCCR - VLPR Clock Control Register */
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
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.divslow = 4, /* DIVSLOW, range 1..16 */
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.divbus = 1, /* DIVBUS, range 1..16 */
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.divcore = 2 /* DIVCORE, range 1..16 */
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.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
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.divslow = 4, /* DIVSLOW, range 1..16 */
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.divbus = 1, /* DIVBUS, range 1..16 */
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.divcore = 2, /* DIVCORE, range 1..16 */
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},
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.hccr =
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.hccr =
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2 /* DIVCORE, range 1..16 */
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2, /* DIVCORE, range 1..16 */
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},
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/* .altclk */
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.initialize = true, /* Initialize */
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.initialize = true, /* Initialize */
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},
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},
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.sim =
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.sim =
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{
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.clockout = /* Clock Out configuration. */
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.clockout = /* Clock Out configuration. */
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{
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.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
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.divider = 1, /* CLKOUTDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = false, /* CLKOUTEN */
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.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
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.divider = 1, /* CLKOUTDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = false, /* CLKOUTEN */
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},
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.lpoclk = /* Low Power Clock configuration. */
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.lpoclk = /* Low Power Clock configuration. */
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{
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.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
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.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
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.initialize = true, /* Initialize */
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.lpo32k = true, /* LPO32KCLKEN */
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.lpo1k = true, /* LPO1KCLKEN */
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.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
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.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
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.initialize = true, /* Initialize */
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.lpo32k = true, /* LPO32KCLKEN */
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.lpo1k = true, /* LPO1KCLKEN */
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},
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.tclk = /* TCLK CLOCK configuration. */
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.tclk = /* TCLK CLOCK configuration. */
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{
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.tclkfreq[0] = 0, /* TCLK0 */
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.tclkfreq[1] = 0, /* TCLK1 */
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.tclkfreq[2] = 0, /* TCLK2 */
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.initialize = true, /* Initialize */
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.tclkfreq[0] = 0, /* TCLK0 */
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.tclkfreq[1] = 0, /* TCLK1 */
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.tclkfreq[2] = 0, /* TCLK2 */
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.initialize = true, /* Initialize */
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},
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.platgate = /* Platform Gate Clock configuration. */
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.platgate = /* Platform Gate Clock configuration. */
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{
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.initialize = true, /* Initialize */
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.mscm = true, /* CGCMSCM */
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.mpu = true, /* CGCMPU */
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.dma = true, /* CGCDMA */
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.erm = true, /* CGCERM */
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.eim = true, /* CGCEIM */
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.initialize = true, /* Initialize */
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.mscm = true, /* CGCMSCM */
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.mpu = true, /* CGCMPU */
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.dma = true, /* CGCDMA */
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.erm = true, /* CGCERM */
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.eim = true, /* CGCEIM */
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},
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.traceclk = /* Debug trace Clock Configuration. */
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.traceclk = /* Debug trace Clock Configuration. */
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{
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.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
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.divider = 1, /* TRACEDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = true, /* TRACEDIVEN */
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.fraction = false, /* TRACEFRAC */
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.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
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.divider = 1, /* TRACEDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = true, /* TRACEDIVEN */
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.fraction = false, /* TRACEFRAC */
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},
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#ifdef CONFIG_S32K1XX_HAVE_QSPI
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.qspirefclk = /* Quad Spi Internal Reference Clock Gating. */
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{
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.refclk = false, /* Qspi reference clock gating */
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},
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#endif
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},
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.pcc =
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.pcc =
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{
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.count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
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.pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */
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.count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
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.pclks = g_peripheral_clockconfig0, /* Peripheral clock configurations */
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},
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.pmc =
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.pmc =
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{
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.lpoclk = /* Low Power Clock configuration. */
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.lpoclk = /* Low Power Clock configuration. */
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{
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.trim = 0, /* Trimming value for LPO */
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.initialize = true, /* Initialize */
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.enable = true, /* Enable/disable LPO */
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.trim = 0, /* Trimming value for LPO */
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.initialize = true, /* Initialize */
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.enable = true, /* Enable/disable LPO */
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},
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}
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},
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};
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -61,14 +61,6 @@
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#include "s32k1xx_periphclocks.h"
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#include "rddrone-uavcan144.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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@ -80,108 +72,79 @@
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const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
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{
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{
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.clkname = ADC0_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_FIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = FLEXCAN0_CLK,
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#ifdef CONFIG_S32K1XX_FLEXCAN
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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},
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{
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.clkname = ADC1_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_FIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = FLEXCAN1_CLK,
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#ifdef CONFIG_S32K1XX_FLEXCAN
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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},
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{
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.clkname = LPI2C0_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = LPI2C0_CLK,
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#ifdef CONFIG_S32K1XX_LPI2C0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPSPI0_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = LPSPI0_CLK,
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#ifdef CONFIG_S32K1XX_LPSPI0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPSPI1_CLK,
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.clkgate = false,
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.clksrc = CLK_SRC_FIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = LPUART0_CLK,
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#ifdef CONFIG_S32K1XX_LPUART0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPSPI2_CLK,
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.clkgate = false,
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.clksrc = CLK_SRC_FIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = LPUART1_CLK,
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#ifdef CONFIG_S32K1XX_LPUART1
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPTMR0_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = PORTA_CLK,
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.clkgate = true,
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},
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{
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.clkname = LPUART0_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = PORTB_CLK,
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.clkgate = true,
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},
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{
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.clkname = LPUART1_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = PORTC_CLK,
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.clkgate = true,
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},
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{
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.clkname = LPUART2_CLK,
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.clkgate = false,
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.clksrc = CLK_SRC_SIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = PORTD_CLK,
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.clkgate = true,
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},
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{
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.clkname = PORTA_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = PORTE_CLK,
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.clkgate = true,
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},
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{
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.clkname = PORTB_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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},
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{
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.clkname = PORTC_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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},
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{
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.clkname = PORTD_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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},
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{
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.clkname = PORTE_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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}
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};
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -86,7 +86,7 @@
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/* Count of peripheral clock user configurations */
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|
||||
#define NUM_OF_PERIPHERAL_CLOCKS_0 15
|
||||
#define NUM_OF_PERIPHERAL_CLOCKS_0 11
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
||||
@ -77,151 +77,141 @@ const struct clock_configuration_s g_initial_clkconfig =
|
||||
{
|
||||
.scg =
|
||||
{
|
||||
.sirc =
|
||||
.sirc =
|
||||
{
|
||||
.range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
|
||||
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
|
||||
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
|
||||
.initialize = true, /* Initialize */
|
||||
.stopmode = true, /* SIRCSTEN */
|
||||
.lowpower = true, /* SIRCLPEN */
|
||||
.locked = false, /* LK */
|
||||
.range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
|
||||
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
|
||||
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
|
||||
.initialize = true, /* Initialize */
|
||||
.stopmode = false, /* SIRCSTEN */
|
||||
.lowpower = true, /* SIRCLPEN */
|
||||
.locked = false, /* LK */
|
||||
},
|
||||
.firc =
|
||||
.firc =
|
||||
{
|
||||
.range = SCG_FIRC_RANGE_48M, /* RANGE */
|
||||
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
|
||||
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
|
||||
.initialize = true, /* Initialize */
|
||||
.stopmode = false, /* */
|
||||
.lowpower = false, /* */
|
||||
.regulator = true, /* FIRCREGOFF */
|
||||
.locked = false, /* LK */
|
||||
.range = SCG_FIRC_RANGE_48M, /* RANGE */
|
||||
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
|
||||
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
|
||||
.initialize = true, /* Initialize */
|
||||
.regulator = true, /* FIRCREGOFF */
|
||||
.locked = false, /* LK */
|
||||
},
|
||||
.sosc =
|
||||
.sosc =
|
||||
{
|
||||
.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
|
||||
.gain = SCG_SOSC_GAIN_LOW, /* HGO */
|
||||
.range = SCG_SOSC_RANGE_MID, /* RANGE */
|
||||
.extref = SCG_SOSC_REF_OSC, /* EREFS */
|
||||
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
|
||||
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
|
||||
.initialize = true, /* Initialize */
|
||||
.stopmode = false, /* */
|
||||
.lowpower = false, /* */
|
||||
.locked = false, /* LK */
|
||||
.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
|
||||
.gain = SCG_SOSC_GAIN_LOW, /* HGO */
|
||||
.range = SCG_SOSC_RANGE_HIGH, /* RANGE */
|
||||
.extref = SCG_SOSC_REF_OSC, /* EREFS */
|
||||
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
|
||||
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
|
||||
.initialize = true, /* Initialize */
|
||||
.locked = false, /* LK */
|
||||
},
|
||||
.spll =
|
||||
.spll =
|
||||
{
|
||||
.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
|
||||
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
|
||||
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
|
||||
.prediv = 1, /* PREDIV */
|
||||
.mult = 40, /* MULT */
|
||||
.src = 0, /* SOURCE */
|
||||
.initialize = true, /* Initialize */
|
||||
.stopmode = false, /* */
|
||||
.locked = false, /* LK */
|
||||
.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
|
||||
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
|
||||
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
|
||||
.prediv = 1, /* PREDIV */
|
||||
.mult = 40, /* MULT */
|
||||
.src = 0, /* SOURCE */
|
||||
.initialize = true, /* Initialize */
|
||||
.locked = false, /* LK */
|
||||
},
|
||||
.rtc =
|
||||
.rtc =
|
||||
{
|
||||
.initialize = true, /* Initialize */
|
||||
.clkin = 0 /* RTC_CLKIN */
|
||||
.initialize = true, /* Initialize */
|
||||
.clkin = 0, /* RTC_CLKIN */
|
||||
},
|
||||
.clockout =
|
||||
.clockout =
|
||||
{
|
||||
.source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
|
||||
.initialize = true, /* Initialize */
|
||||
.source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
|
||||
.initialize = true, /* Initialize */
|
||||
},
|
||||
.clockmode =
|
||||
.clockmode =
|
||||
{
|
||||
.rccr = /* RCCR - Run Clock Control Register */
|
||||
.rccr = /* RCCR - Run Clock Control Register */
|
||||
{
|
||||
.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
|
||||
.divslow = 3, /* DIVSLOW, range 1..16 */
|
||||
.divbus = 2, /* DIVBUS, range 1..16 */
|
||||
.divcore = 2 /* DIVCORE, range 1..16 */
|
||||
.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
|
||||
.divslow = 3, /* DIVSLOW, range 1..16 */
|
||||
.divbus = 2, /* DIVBUS, range 1..16 */
|
||||
.divcore = 2, /* DIVCORE, range 1..16 */
|
||||
},
|
||||
.vccr = /* VCCR - VLPR Clock Control Register */
|
||||
.vccr = /* VCCR - VLPR Clock Control Register */
|
||||
{
|
||||
.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
|
||||
.divslow = 4, /* DIVSLOW, range 1..16 */
|
||||
.divbus = 1, /* DIVBUS, range 1..16 */
|
||||
.divcore = 2 /* DIVCORE, range 1..16 */
|
||||
.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
|
||||
.divslow = 4, /* DIVSLOW, range 1..16 */
|
||||
.divbus = 1, /* DIVBUS, range 1..16 */
|
||||
.divcore = 2, /* DIVCORE, range 1..16 */
|
||||
},
|
||||
.hccr =
|
||||
.hccr =
|
||||
{
|
||||
.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
|
||||
.divslow = 3, /* DIVSLOW, range 1..16 */
|
||||
.divbus = 2, /* DIVBUS, range 1..16 */
|
||||
.divcore = 2 /* DIVCORE, range 1..16 */
|
||||
.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
|
||||
.divslow = 3, /* DIVSLOW, range 1..16 */
|
||||
.divbus = 2, /* DIVBUS, range 1..16 */
|
||||
.divcore = 2, /* DIVCORE, range 1..16 */
|
||||
},
|
||||
|
||||
/* .altclk */
|
||||
|
||||
.initialize = true, /* Initialize */
|
||||
.initialize = true, /* Initialize */
|
||||
},
|
||||
},
|
||||
.sim =
|
||||
.sim =
|
||||
{
|
||||
.clockout = /* Clock Out configuration. */
|
||||
.clockout = /* Clock Out configuration. */
|
||||
{
|
||||
.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
|
||||
.divider = 1, /* CLKOUTDIV, range 1..8 */
|
||||
.initialize = true, /* Initialize */
|
||||
.enable = false, /* CLKOUTEN */
|
||||
.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
|
||||
.divider = 1, /* CLKOUTDIV, range 1..8 */
|
||||
.initialize = true, /* Initialize */
|
||||
.enable = false, /* CLKOUTEN */
|
||||
},
|
||||
.lpoclk = /* Low Power Clock configuration. */
|
||||
.lpoclk = /* Low Power Clock configuration. */
|
||||
{
|
||||
.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
|
||||
.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
|
||||
.initialize = true, /* Initialize */
|
||||
.lpo32k = true, /* LPO32KCLKEN */
|
||||
.lpo1k = true, /* LPO1KCLKEN */
|
||||
.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
|
||||
.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
|
||||
.initialize = true, /* Initialize */
|
||||
.lpo32k = true, /* LPO32KCLKEN */
|
||||
.lpo1k = true, /* LPO1KCLKEN */
|
||||
},
|
||||
.tclk = /* TCLK CLOCK configuration. */
|
||||
.tclk = /* TCLK CLOCK configuration. */
|
||||
{
|
||||
.tclkfreq[0] = 0, /* TCLK0 */
|
||||
.tclkfreq[1] = 0, /* TCLK1 */
|
||||
.tclkfreq[2] = 0, /* TCLK2 */
|
||||
.initialize = true, /* Initialize */
|
||||
.tclkfreq[0] = 0, /* TCLK0 */
|
||||
.tclkfreq[1] = 0, /* TCLK1 */
|
||||
.tclkfreq[2] = 0, /* TCLK2 */
|
||||
.initialize = true, /* Initialize */
|
||||
},
|
||||
.platgate = /* Platform Gate Clock configuration. */
|
||||
.platgate = /* Platform Gate Clock configuration. */
|
||||
{
|
||||
.initialize = true, /* Initialize */
|
||||
.mscm = true, /* CGCMSCM */
|
||||
.mpu = true, /* CGCMPU */
|
||||
.dma = true, /* CGCDMA */
|
||||
.erm = true, /* CGCERM */
|
||||
.eim = true, /* CGCEIM */
|
||||
.initialize = true, /* Initialize */
|
||||
.mscm = true, /* CGCMSCM */
|
||||
.mpu = true, /* CGCMPU */
|
||||
.dma = true, /* CGCDMA */
|
||||
.erm = true, /* CGCERM */
|
||||
.eim = true, /* CGCEIM */
|
||||
},
|
||||
.traceclk = /* Debug trace Clock Configuration. */
|
||||
.traceclk = /* Debug trace Clock Configuration. */
|
||||
{
|
||||
.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
|
||||
.divider = 1, /* TRACEDIV, range 1..8 */
|
||||
.initialize = true, /* Initialize */
|
||||
.enable = true, /* TRACEDIVEN */
|
||||
.fraction = false, /* TRACEFRAC */
|
||||
.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
|
||||
.divider = 1, /* TRACEDIV, range 1..8 */
|
||||
.initialize = true, /* Initialize */
|
||||
.enable = true, /* TRACEDIVEN */
|
||||
.fraction = false, /* TRACEFRAC */
|
||||
},
|
||||
#ifdef CONFIG_S32K1XX_HAVE_QSPI
|
||||
.qspirefclk = /* Quad Spi Internal Reference Clock Gating. */
|
||||
{
|
||||
.refclk = false, /* Qspi reference clock gating */
|
||||
},
|
||||
#endif
|
||||
},
|
||||
.pcc =
|
||||
.pcc =
|
||||
{
|
||||
.count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
|
||||
.pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */
|
||||
.count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
|
||||
.pclks = g_peripheral_clockconfig0, /* Peripheral clock configurations */
|
||||
},
|
||||
.pmc =
|
||||
.pmc =
|
||||
{
|
||||
.lpoclk = /* Low Power Clock configuration. */
|
||||
.lpoclk = /* Low Power Clock configuration. */
|
||||
{
|
||||
.trim = 0, /* Trimming value for LPO */
|
||||
.initialize = true, /* Initialize */
|
||||
.enable = true, /* Enable/disable LPO */
|
||||
.trim = 0, /* Trimming value for LPO */
|
||||
.initialize = true, /* Initialize */
|
||||
.enable = true, /* Enable/disable LPO */
|
||||
},
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
@ -61,14 +61,6 @@
|
||||
#include "s32k1xx_periphclocks.h"
|
||||
#include "rddrone-uavcan146.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
@ -80,108 +72,79 @@
|
||||
const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
|
||||
{
|
||||
{
|
||||
.clkname = ADC0_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_FIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = FLEXCAN0_CLK,
|
||||
#ifdef CONFIG_S32K1XX_FLEXCAN
|
||||
.clkgate = true,
|
||||
#else
|
||||
.clkgate = false,
|
||||
#endif
|
||||
},
|
||||
{
|
||||
.clkname = ADC1_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_FIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = FLEXCAN1_CLK,
|
||||
#ifdef CONFIG_S32K1XX_FLEXCAN
|
||||
.clkgate = true,
|
||||
#else
|
||||
.clkgate = false,
|
||||
#endif
|
||||
},
|
||||
{
|
||||
.clkname = LPI2C0_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = LPI2C0_CLK,
|
||||
#ifdef CONFIG_S32K1XX_LPI2C0
|
||||
.clkgate = true,
|
||||
#else
|
||||
.clkgate = false,
|
||||
#endif
|
||||
.clksrc = CLK_SRC_SIRC_DIV2,
|
||||
},
|
||||
{
|
||||
.clkname = LPSPI0_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = LPSPI0_CLK,
|
||||
#ifdef CONFIG_S32K1XX_LPSPI0
|
||||
.clkgate = true,
|
||||
#else
|
||||
.clkgate = false,
|
||||
#endif
|
||||
.clksrc = CLK_SRC_SIRC_DIV2,
|
||||
},
|
||||
{
|
||||
.clkname = LPSPI1_CLK,
|
||||
.clkgate = false,
|
||||
.clksrc = CLK_SRC_FIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = LPUART0_CLK,
|
||||
#ifdef CONFIG_S32K1XX_LPUART0
|
||||
.clkgate = true,
|
||||
#else
|
||||
.clkgate = false,
|
||||
#endif
|
||||
.clksrc = CLK_SRC_SIRC_DIV2,
|
||||
},
|
||||
{
|
||||
.clkname = LPSPI2_CLK,
|
||||
.clkgate = false,
|
||||
.clksrc = CLK_SRC_FIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = LPUART1_CLK,
|
||||
#ifdef CONFIG_S32K1XX_LPUART1
|
||||
.clkgate = true,
|
||||
#else
|
||||
.clkgate = false,
|
||||
#endif
|
||||
.clksrc = CLK_SRC_SIRC_DIV2,
|
||||
},
|
||||
{
|
||||
.clkname = LPTMR0_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = PORTA_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
{
|
||||
.clkname = LPUART0_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = PORTB_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
{
|
||||
.clkname = LPUART1_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = PORTC_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
{
|
||||
.clkname = LPUART2_CLK,
|
||||
.clkgate = false,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = PORTD_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
{
|
||||
.clkname = PORTA_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = PORTE_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
{
|
||||
.clkname = PORTB_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
},
|
||||
{
|
||||
.clkname = PORTC_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
},
|
||||
{
|
||||
.clkname = PORTD_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
},
|
||||
{
|
||||
.clkname = PORTE_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
}
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user