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LPC31 EHCI: First cut at an EHCI driver for the LPC31

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This commit is contained in:
Gregory Nutt 2013-11-14 16:12:22 -06:00
parent ca61cba028
commit 9680043a46
2 changed files with 4351 additions and 2 deletions
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4344
arch/arm/src/lpc31xx/lpc31_ehci.c Executable file
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File diff suppressed because it is too large Load Diff

9
arch/arm/src/lpc31xx/lpc31_usbotg.h
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@ -58,8 +58,9 @@
/* 0x000 - 0x0ff: Reserved */
/* Device/host capability registers */
#define LPC31_USBOTG_CAPLENGTH_OFFSET 0x100 /* Capability register length */
#define LPC31_USBHOST_HCIVERSION_OFFSET 0x102 /* Host interface version number */
#define LPC31_USBOTG_HCCR_OFFSET 0x100 /* Offset to EHCI Host Controller Capabiliy registers */
#define LPC31_USBOTG_CAPLENGTH_OFFSET 0x100 /* Capability register length (8-bit) */
#define LPC31_USBHOST_HCIVERSION_OFFSET 0x102 /* Host interface version number (16-bit) */
#define LPC31_USBHOST_HCSPARAMS_OFFSET 0x104 /* Host controller structural parameters */
#define LPC31_USBHOST_HCCPARAMS_OFFSET 0x108 /* Host controller capability parameters */
#define LPC31_USBDEV_DCIVERSION_OFFSET 0x120 /* Device interface version number */
@ -67,10 +68,12 @@
/* Device/host/OTG operational registers */
#define LPC31_USBOTG_HCOR_OFFSET 0x140 /* Offset to EHCI Host Controller Operational Registers */
#define LPC31_USBOTG_USBCMD_OFFSET 0x140 /* USB command (both) */
#define LPC31_USBOTG_USBSTS_OFFSET 0x144 /* USB status (both) */
#define LPC31_USBOTG_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define LPC31_USBOTG_FRINDEX_OFFSET 0x14C /* USB frame index (both) */
/* EHCI 4G Segment Selector (not supported) */
#define LPC31_USBOTG_PERIODICLIST_OFFSET 0x154 /* Frame list base address (host) */
#define LPC31_USBOTG_DEVICEADDR_OFFSET 0x154 /* USB device address (device) */
#define LPC31_USBOTG_ASYNCLISTADDR_OFFSET 0x158 /* Next asynchronous list address (host) */
@ -128,6 +131,7 @@
/* Device/host capability registers */
#define LPC31_USBOTG_HCCR_BASE (LPC31_USBOTG_VBASE+LPC31_USBOTG_HCCR_OFFSET)
#define LPC31_USBOTG_CAPLENGTH (LPC31_USBOTG_VBASE+LPC31_USBOTG_CAPLENGTH_OFFSET)
#define LPC31_USBHOST_HCIVERSION (LPC31_USBOTG_VBASE+LPC31_USBHOST_HCIVERSION_OFFSET)
#define LPC31_USBHOST_HCSPARAMS (LPC31_USBOTG_VBASE+LPC31_USBHOST_HCSPARAMS_OFFSET)
@ -137,6 +141,7 @@
/* Device/host operational registers */
#define LPC31_USBOTG_HCOR_BASE (LPC31_USBOTG_VBASE+LPC31_USBOTG_HCOR_OFFSET)
#define LPC31_USBOTG_USBCMD (LPC31_USBOTG_VBASE+LPC31_USBOTG_USBCMD_OFFSET)
#define LPC31_USBOTG_USBSTS (LPC31_USBOTG_VBASE+LPC31_USBOTG_USBSTS_OFFSET)
#define LPC31_USBOTG_USBINTR (LPC31_USBOTG_VBASE+LPC31_USBOTG_USBINTR_OFFSET)