Add missing TWI definitions

arch/arm/src/sam34/chip/sam3x_memorymap.h

@@ -91,6 +91,7 @@
 #  define SAM_TC8_BASE         0x40088080 /* 0x40088080-0x400880bf:   Timer Counter 5 */
                                           /* 0x400880c0-0x4008ffff    Reserved */
 #define SAM_TWI_BASE           0x4008c000 /* 0x4008c000-0x4001ffff: Two-Wire Interface */
+#  define SAM_TWIN_BASE(n)     (SAM_TWI_BASE + ((n) << 14))
 #  define SAM_TWI0_BASE        0x4008c000 /* 0x4008c000-0x4008ffff:   Two-Wire Interface 0 */
 #  define SAM_TWI1_BASE        0x40090000 /* 0x40090000-0x40093fff:   Two-Wire Interface 1 */
 #define SAM_PWM_BASE           0x40094000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */

arch/arm/src/sam34/chip/sam4cm_memorymap.h

@@ -77,8 +77,12 @@
 #define SAM_TC3_BASE           0x40014000
 #define SAM_TC4_BASE           0x40014040
 #define SAM_TC5_BASE           0x40014080
+
+#define SAM_TWI_BASE           0x40018000
+#define SAM_TWIN_BASE(n)       (SAM_TWI_BASE + ((n) << 14))
 #define SAM_TWI0_BASE          0x40018000
 #define SAM_TWI1_BASE          0x4001C000
+
 #define SAM_USART0_BASE        0x40024000
 #define SAM_USART1_BASE        0x40028000
 #define SAM_USART2_BASE        0x4002C000

arch/arm/src/sam34/chip/sam4e_memorymap.h

@@ -108,6 +108,7 @@
 #  define SAM_USART0_BASE      0x400a0000 /* 0x400a0000-0x400a3fff:   USART0 */
 #  define SAM_USART1_BASE      0x400a4000 /* 0x400a4000-0x400abfff:   USART1 */
 #define SAM_TWI_BASE           0x400a8000 /* 0x400a8000-0x400affff: Two-Wire Interface */
+#  define SAM_TWIN_BASE(n)     (SAM_TWI_BASE + ((n) << 14))
 #  define SAM_TWI0_BASE        0x400a8000 /* 0x400a8000-0x400abfff:   Two-Wire Interface 0 */
 #  define SAM_TWI1_BASE        0x400ac000 /* 0x400ac000-0x400affff:   Two-Wire Interface 1 */
 #define SAM_AFEC_BASE          0x400b0000 /* 0x400b0000-0x400b7fff: Analog Front End */

arch/arm/src/sam34/chip/sam4l_memorymap.h

@@ -82,6 +82,9 @@
                                         /* 0x4000c000-0x4000ffff: Reserved */
 #define SAM_TC0_BASE         0x40100000 /* 0x40100000-0x4013ffff: Timer Counter 0 */
 #define SAM_TC1_BASE         0x40140000 /* 0x40180000-0x4017ffff: Timer Counter 1 */
+
+#define SAM_TWIMS_BASE       0x40180000 /* 0x40180000-0x401fffff: Two-wire Master/Slave */
+#define SAM_TWIN_BASE(n)     (SAM_TWIMS_BASE + ((n) << 14))
 #define SAM_TWIMS0_BASE      0x40180000 /* 0x40180000-0x401bffff: Two-wire Master/Slave Interface 0 */
 #define SAM_TWIMS1_BASE      0x401c0000 /* 0x401c0000-0x401fffff: Two-wire Master/Slave Interface 1 */
                                         /* 0x40020000-0x40023fff: Reserved */

arch/arm/src/sam34/chip/sam4s_memorymap.h

@@ -84,6 +84,7 @@
 #  define SAM_TC5_BASE         0x40014080 /* 0x40014080-0x400140bf:   Timer Counter 5 */
 
 #define SAM_TWI_BASE           0x40018000 /* 0x40018000-0x4001ffff: Two-Wire Interface */
+#  define SAM_TWIN_BASE(n)     (SAM_TWI_BASE + ((n) << 14))
 #  define SAM_TWI0_BASE        0x40018000 /* 0x40018000-0x4001bfff:   Two-Wire Interface 0 */
 #  define SAM_TWI1_BASE        0x4001c000 /* 0x4001c000-0x4001ffff:   Two-Wire Interface 1 */
 #define SAM_PWM_BASE           0x40020000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */

arch/arm/src/sam34/chip/sam_twi.h

@@ -143,6 +143,7 @@
 #define TWI_MMR_MREAD              (1 << 12) /* Bit 12: Master Read Direction */
 #define TWI_MMR_DADR_SHIFT         (16)      /* Bits 16-22:  Device Address */
 #define TWI_MMR_DADR_MASK          (0x7f << TWI_MMR_DADR_SHIFT)
+#  define TWI_MMR_DADR(n)          ((uint32_t)(n) << TWI_MMR_DADR_SHIFT)
 
 /* TWI Slave Mode Register */
 
@@ -186,6 +187,9 @@
 #define TWI_INT_RXBUFF             (1 << 14) /* Bit 14: RX Buffer */
 #define TWI_INT_TXBUFE             (1 << 15) /* Bit 15: TX Buffer Empty */
 
+#define TWI_INT_ERRORS             (0x00000340)
+#define TWI_INT_ALL                (0x0000ffff)
+
 /* TWI Receive Holding Register */
 
 #define TWI_RHR_RXDATA_SHIFT       (0)       /* Bits 0-7:  Master or Slave Receive Holding Data */