Beginnings of lpc313x CGU driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2438 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
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96e13d651d
@ -45,5 +45,8 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
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up_sigdeliver.c up_syscall.c up_unblocktask.c \
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up_undefinedinsn.c up_usestack.c
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CGU_ASRCS =
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CGU_CSRCS = lpc313x_clkdomain.c
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CHIP_ASRCS =
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CHIP_CSRCS = lpc313x_irq.c lpc313x_allocateheap.c
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CHIP_CSRCS = lpc313x_irq.c lpc313x_allocateheap.c $(CGU_CSRCS)
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@ -4,6 +4,9 @@
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* References:
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* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -1601,172 +1604,11 @@
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#define CGU_HP1SELP_SHIFT (0) /* Bits 0-4: Bandwidth selection register of HP1 PLL */
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#define CGU_HP1IELP_MASK (31 << CGU_HP1SELP_SHIFT)
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/* Clock ID ranges (see enum lpc313x_clockid_e) *************************************************/
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#define CLKID_SYSBASE_FIRST CLKID_APB0CLK /* Domain 0: SYS_BASE */
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#define CLKID_SYSBASE_LAST CLKID_INTCCLK
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#define CLKID_AHB0APB0_FIRST CLKID_AHB2APB0ASYNCPCLK /* Domain 1: AHB0APB0_BASE */
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#define CLKID_AHB0APB0_LAST CLKID_RNGPCLK
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#define CLKID_AHB0APB1_FIRST CLKID_AHB2APB1ASYNCPCLK /* Domain 2: AHB0APB1_BASE */
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#define CLKID_AHB0APB1_LAST CLKID_I2C1PCLK
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#define CLKID_AHB0APB2_FIRST CLKID_AHB2APB2ASYNCPCLK /* Domain 3: AHB0APB2_BASE */
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#define CLKID_AHB0APB2_LAST CLKID_SPIPCLKGATED
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#define CLKID_AHB0APB3_FIRST CLKID_AHB2APB3PCLK /* Domain 4: AHB0APB3_BASE */
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#define CLKID_AHB0APB3_LAST CLKID_RESERVED70
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#define CLKID_PCM_FIRST CLKID_PCMCLKIP /* Domain 5: PCM_BASE */
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#define CLKID_PCM_LAST CLKID_PCMCLKIP
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#define CLKID_UART_FIRST CLKID_UARTUCLK /* Domain 6: UART_BASE */
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#define CLKID_UART_LAST CLKID_UARTUCLK
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#define CLKID_CLK1024FS_FIRST CLKID_I2SEDGEDETECTCLK /* Domain 7: CLK1024FS_BASE */
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#define CLKID_CLK1024FS_LAST CLKID_RESERVED86
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#define CLKID_I2SRXBCK0_FIRST CLKID_I2SRXBCK0 /* Domain 8: BCK0_BASE */
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#define CLKID_I2SRXBCK0_LAST CLKID_I2SRXBCK0
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#define CLKID_I2SRXBCK1_FIRST CLKID_I2SRXBCK1 /* Domain 9: BCK1_BASE */
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#define CLKID_I2SRXBCK1_LAST CLKID_I2SRXBCK1
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#define CLKID_SPI_FIRST CLKID_SPICLK /* Domain 10: SPI_BASE */
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#define CLKID_SPI_LAST CLKID_SPICLKGATED
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#define CLKID_SYSCLKO_FIRST CLKID_SYSCLKO /* Domain 11: SYSCLKO_BASE */
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#define CLKID_SYSCLKO_LAST CLKID_SYSCLKO
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#define CLKID_INVALIDCLK -1
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/************************************************************************************************
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* Public Types
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************************************************************************************************/
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#ifndef __ASSEMBLY__
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/* Clock IDs -- These are indices corresponding to the register offsets above */
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enum lpc313x_clockid_e
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{
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/* Domain 0: SYS_BASE */
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CLKID_APB0CLK = 0, /* 0 APB0_CLK */
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CLKID_SBAPB1CLK, /* 1 APB1_CLK */
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CLKID_APB2CLK, /* 2 APB2_CLK */
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CLKID_APB3CLK, /* 3 APB3_CLK */
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CLKID_APB4CLK, /* 4 APB4_CLK */
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CLKID_AHB2INTCCLK, /* 5 AHB_TO_INTC_CLK */
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CLKID_AHB0CLK, /* 6 AHB0_CLK */
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CLKID_EBICLK, /* 7 EBI_CLK */
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CLKID_DMAPCLK, /* 8 DMA_PCLK */
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CLKID_DMACLKGATED, /* 9 DMA_CLK_GATED */
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CLKID_NANDFLASHS0CLK, /* 10 NANDFLASH_S0_CLK */
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CLKID_NANDFLASHECCCLK, /* 11 NANDFLASH_ECC_CLK */
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CLKID_NANDFLASHAESCLK, /* 12 NANDFLASH_AES_CLK (Reserved on LPC313x) */
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CLKID_NANDFLASHNANDCLK, /* 13 NANDFLASH_NAND_CLK */
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CLKID_NANDFLASHPCLK, /* 14 NANDFLASH_PCLK */
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CLKID_CLOCKOUT, /* 15 CLOCK_OUT */
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CLKID_ARM926CORECLK, /* 16 ARM926_CORE_CLK */
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CLKID_ARM926BUSIFCLK, /* 17 ARM926_BUSIF_CLK */
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CLKID_ARM926RETIMECLK, /* 18 ARM926_RETIME_CLK */
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CLKID_SDMMCHCLK, /* 19 SD_MMC_HCLK */
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CLKID_SDMMCCCLKIN, /* 20 SD_MMC_CCLK_IN */
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CLKID_USBOTGAHBCLK, /* 21 USB_OTG_AHB_CLK */
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CLKID_ISRAM0CLK, /* 22 ISRAM0_CLK */
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CLKID_REDCTLRSCLK, /* 23 RED_CTL_RSCLK */
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CLKID_ISRAM1CLK, /* 24 ISRAM1_CLK (LPC313x only) */
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CLKID_ISROMCLK, /* 25 ISROM_CLK */
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CLKID_MPMCCFGCLK, /* 26 MPMC_CFG_CLK */
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CLKID_MPMCCFGCLK2, /* 27 MPMC_CFG_CLK2 */
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CLKID_MPMCCFGCLK3, /* 28 MPMC_CFG_CLK3 */
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CLKID_INTCCLK, /* 29 INTC_CLK */
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/* Domain 1: AHB0APB0BASE */
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CLKID_AHB2APB0PCLK, /* 30 AHB_TO_APB0_PCLK */
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CLKID_EVENTROUTERPCLK, /* 31 EVENT_ROUTER_PCLK */
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CLKID_ADCPCLK, /* 32 ADC_PCLK */
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CLKID_ADCCLK, /* 33 ADC_CLK */
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CLKID_WDOGPCLK, /* 34 WDOG_PCLK */
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CLKID_IOCONFPCLK, /* 35 IOCONF_PCLK */
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CLKID_CGUPCLK, /* 36 CGU_PCLK */
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CLKID_SYSCREGPCLK, /* 37 SYSCREG_PCLK */
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CLKID_OTPPCLK, /* 38 OTP_PCLK (Reserved on LPC313X) */
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CLKID_RNGPCLK, /* 39 RNG_PCLK */
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/* Domain 2: AHB0APB1BASE */
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CLKID_AHB2APB1PCLK, /* 40 AHB_TO_APB1_PCLK */
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CLKID_TIMER0PCLK, /* 41 TIMER0_PCLK */
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CLKID_TIMER1PCLK, /* 42 TIMER1_PCLK */
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CLKID_TIMER2PCLK, /* 43 TIMER2_PCLK */
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CLKID_TIMER3PCLK, /* 44 TIMER3_PCLK */
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CLKID_PWMPCLK, /* 45 PWM_PCLK */
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CLKID_PWMPCLKREGS, /* 46 PWM_PCLK_REGS */
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CLKID_PWMCLK, /* 47 PWM_CLK */
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CLKID_I2C0PCLK, /* 48 I2C0_PCLK */
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CLKID_I2C1PCLK, /* 49 I2C1_PCLK */
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/* Domain 3: AHB0APB2BASE */
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CLKID_AHB2APB2PCLK, /* 50 AHB_TO_APB2_PCLK */
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CLKID_PCMPCLK, /* 51 PCM_PCLK */
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CLKID_PCMAPBPCLK, /* 52 PCM_APB_PCLK */
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CLKID_UARTAPBCLK, /* 53 UART_APB_CLK */
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CLKID_LCDPCLK, /* 54 LCD_PCLK */
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CLKID_LCDCLK, /* 55 LCD_CLK */
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CLKID_SPIPCLK, /* 56 SPI_PCLK */
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CLKID_SPIPCLKGATED, /* 57 SPI_PCLK_GATED */
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/* Domain 4: AHB0APB3BASE */
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CLKID_AHB2APB3PCLK, /* 58 AHB_TO_APB3_PCLK */
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CLKID_I2SCFGPCLK, /* 59 I2S_CFG_PCLK */
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CLKID_EDGEDETPCLK, /* 60 EDGE_DET_PCLK */
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CLKID_I2STXFIFO0PCLK, /* 61 I2STX_FIFO_0_PCLK */
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CLKID_I2STXIF0PCLK, /* 62 I2STX_IF_0_PCLK */
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CLKID_I2STXFIFO1PCLK, /* 63 I2STX_FIFO_1_PCLK */
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CLKID_I2STXIF1PCLK, /* 64 I2STX_IF_1_PCLK */
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CLKID_I2SRXFIFO0PCLK, /* 65 I2SRX_FIFO_0_PCLK */
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CLKID_I2SRXIF0PCLK, /* 66 I2SRX_IF_0_PCLK */
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CLKID_I2SRXFIFO1PCLK, /* 67 I2SRX_FIFO_1_PCLK */
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CLKID_I2SRXIF1PCLK, /* 68 I2SRX_IF_1_PCLK */
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CLKID_RESERVED69, /* 69 Reserved */
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CLKID_RESERVED70, /* 70 Reserved */
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/* Domain 5: PCM_BASE */
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CLKID_PCMCLKIP, /* 71 PCM_CLK_IP */
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/* Domain 6: UART_BASE */
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CLKID_UARTUCLK, /* 72 UART_U_CLK */
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/* Domain 7: CLK1024FS_BASE */
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CLKID_I2SEDGEDETECTCLK, /* 73 I2S_EDGE_DETECT_CLK */
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CLKID_I2STXBCK0N, /* 74 I2STX_BCK0_N */
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CLKID_I2STXWS0, /* 75 I2STX_WS0 */
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CLKID_I2STXCLK0, /* 76 I2STX_CLK0 */
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CLKID_I2STXBCK1N, /* 77 I2STX_BCK1_N */
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CLKID_I2STXWS1, /* 78 I2STX_WS1 */
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CLKID_CLK256FS, /* 79 CLK_256FS */
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CLKID_I2SRXBCK0N, /* 80 I2SRX_BCK0_N */
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CLKID_I2SRXWS0, /* 81 I2SRX_WS0 */
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CLKID_I2SRXBCK1N, /* 82 I2SRX_BCK1_N */
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CLKID_I2SRXWS1, /* 83 I2SRX_WS1 */
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CLKID_RESERVED84, /* 84 Reserved */
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CLKID_RESERVED85, /* 85 Reserved */
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CLKID_RESERVED86, /* 86 Reserved */
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/* Domain 8: BCK0_BASE */
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CLKID_I2SRXBCK0, /* 87 I2SRX_BCK0 */
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/* Domain 9: BCK1_BASE */
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CLKID_I2SRXBCK1, /* 88 I2SRX_BCK1 */
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/* Domain 10: SPI_BASE */
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CLKID_SPICLK, /* 89 SPI_CLK */
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CLKID_SPICLKGATED, /* 90 SPI_CLK_GATED */
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/* Domain 11: SYSCLKO_BASE */
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CLKID_SYSCLKO /* 91 SYSCLK_O */
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};
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/************************************************************************************************
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* Public Data
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************************************************************************************************/
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@ -1775,28 +1617,6 @@ enum lpc313x_clockid_e
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* Inline Functions
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************************************************************************************************/
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/* Enable the specified clock */
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static inline void lpc313x_enableclock(enum lpc313x_clockid_e clkid)
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{
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uint32_t address = LPC313X_CGU_PCR((int)clkid);
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uint32_t regval = getreg32(address);
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regval |= CGU_PCR_RUN;
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putreg32(regval, address);
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}
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/* Disable the specified clock */
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static inline void lpc313x_disableclock(enum lpc313x_clockid_e clkid)
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{
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uint32_t address = LPC313X_CGU_PCR((int)clkid);
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uint32_t regval = getreg32(address);
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regval &= ~CGU_PCR_RUN;
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putreg32(regval, address);
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}
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/************************************************************************************************
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* Public Functions
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************************************************************************************************/
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385
arch/arm/src/lpc313x/lpc313x_cgudrvr.h
Executable file
385
arch/arm/src/lpc313x/lpc313x_cgudrvr.h
Executable file
@ -0,0 +1,385 @@
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/************************************************************************
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* arch/arm/src/lpc313x/lpc313x_cgudrvr.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* References:
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* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
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* - lpc313x.cdl.drivers.zip example driver code
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC313X_CGUDRVR_H
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#define __ARCH_ARM_SRC_LPC313X_CGUDRVR_H
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/************************************************************************
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* Included Files
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************************************************************************/
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#include <nuttx/config.h>
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#include "lpc313x_cgu.h"
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/************************************************************************
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* Pre-processor Definitions
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************************************************************************/
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/* Maps a valid, x, relative to a base value, b, and converts that to a bit position */
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#define _RBIT(x,b) (1<<((x)-(b)))
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/* Clock ID ranges (see enum lpc313x_clockid_e) *************************************************/
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#define CLKID_SYSBASE_FIRST CLKID_APB0CLK /* Domain 0: SYS_BASE */
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#define CLKID_SYSBASE_LAST CLKID_INTCCLK
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#define _D0B(id) _RBIT(id,CLKID_SYSBASE_FIRST)
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#define CLKID_AHB0APB0_FIRST CLKID_AHB2APB0ASYNCPCLK /* Domain 1: AHB0APB0_BASE */
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#define CLKID_AHB0APB0_LAST CLKID_RNGPCLK
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#define _D1B(id) _RBIT(id,CLKID_AHB0APB0_FIRST)
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#define CLKID_AHB0APB1_FIRST CLKID_AHB2APB1ASYNCPCLK /* Domain 2: AHB0APB1_BASE */
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#define CLKID_AHB0APB1_LAST CLKID_I2C1PCLK
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#define _D2B(id) _RBIT(id,CLKID_AHB0APB1_FIRST)
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#define CLKID_AHB0APB2_FIRST CLKID_AHB2APB2ASYNCPCLK /* Domain 3: AHB0APB2_BASE */
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#define CLKID_AHB0APB2_LAST CLKID_SPIPCLKGATED
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#define _D3B(id) _RBIT(id,CLKID_AHB0APB2_FIRST)
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#define CLKID_AHB0APB3_FIRST CLKID_AHB2APB3PCLK /* Domain 4: AHB0APB3_BASE */
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#define CLKID_AHB0APB3_LAST CLKID_RESERVED70
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#define _D4B(id) _RBIT(id,CLKID_AHB0APB3_FIRST)
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#define CLKID_PCM_FIRST CLKID_PCMCLKIP /* Domain 5: PCM_BASE */
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#define CLKID_PCM_LAST CLKID_PCMCLKIP
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#define _D5B(id) _RBIT(id,CLKID_PCM_FIRST)
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#define CLKID_UART_FIRST CLKID_UARTUCLK /* Domain 6: UART_BASE */
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#define CLKID_UART_LAST CLKID_UARTUCLK
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#define _D6B(id) _RBIT(id,CLKID_UART_FIRST)
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#define CLKID_CLK1024FS_FIRST CLKID_I2SEDGEDETECTCLK /* Domain 7: CLK1024FS_BASE */
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#define CLKID_CLK1024FS_LAST CLKID_RESERVED86
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#define _D7B(id) _RBIT(id,CLKID_CLK1024FS_FIRST)
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#define CLKID_I2SRXBCK0_FIRST CLKID_I2SRXBCK0 /* Domain 8: BCK0_BASE */
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#define CLKID_I2SRXBCK0_LAST CLKID_I2SRXBCK0
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#define _D8B(id) _RBIT(id,CLKID_I2SRXBCK0_FIRST)
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#define CLKID_I2SRXBCK1_FIRST CLKID_I2SRXBCK1 /* Domain 9: BCK1_BASE */
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#define CLKID_I2SRXBCK1_LAST CLKID_I2SRXBCK1
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#define _D9B(id) _RBIT(id,CLKID_SYSBASE_FIRST)
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#define CLKID_SPI_FIRST CLKID_SPICLK /* Domain 10: SPI_BASE */
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#define CLKID_SPI_LAST CLKID_SPICLKGATED
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#define _D10B(id) _RBIT(id,CLKID_I2SRXBCK1_FIRST)
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#define CLKID_SYSCLKO_FIRST CLKID_SYSCLKO /* Domain 11: SYSCLKO_BASE */
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#define CLKID_SYSCLKO_LAST CLKID_SYSCLKO
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#define _D11B(id) _RBIT(id,CLKID_SYSCLKO_FIRST)
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#define CGU_NDOMAINS 12
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#define CLKID_INVALIDCLK -1
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#define CLKID_INVALIDDOMAIN -1
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/* The number of fractional dividers available for each base frequency,
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* their bit widths and extractions for sub elements from the fractional
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* divider configuration register
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*/
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#define FRACDIV_BASE0_CNT 7
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#define FRACDIV_BASE0_LOW 0
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#define FRACDIV_BASE0_HIGH 6
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#define FRACDIV_BASE0_FDIV0W 8
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#define FRACDIV_BASE1_CNT 2
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#define FRACDIV_BASE1_LOW 7
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#define FRACDIV_BASE1_HIGH 8
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#define FRACDIV_BASE1_FDIV0W 8
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#define FRACDIV_BASE2_CNT 2
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#define FRACDIV_BASE2_LOW 9
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#define FRACDIV_BASE2_HIGH 10
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#define FRACDIV_BASE2_FDIV0W 8
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#define FRACDIV_BASE3_CNT 3
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#define FRACDIV_BASE3_LOW 11
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#define FRACDIV_BASE3_HIGH 13
|
||||
#define FRACDIV_BASE3_FDIV0W 8
|
||||
|
||||
#define FRACDIV_BASE4_CNT 1
|
||||
#define FRACDIV_BASE4_LOW 14
|
||||
#define FRACDIV_BASE4_HIGH 14
|
||||
#define FRACDIV_BASE4_FDIV0W 8
|
||||
|
||||
#define FRACDIV_BASE5_CNT 1
|
||||
#define FRACDIV_BASE5_LOW 15
|
||||
#define FRACDIV_BASE5_HIGH 15
|
||||
#define FRACDIV_BASE5_FDIV0W 8
|
||||
|
||||
#define FRACDIV_BASE6_CNT 1
|
||||
#define FRACDIV_BASE6_LOW 16
|
||||
#define FRACDIV_BASE6_HIGH 16
|
||||
#define FRACDIV_BASE6_FDIV0W 8
|
||||
|
||||
#define FRACDIV_BASE7_CNT 6
|
||||
#define FRACDIV_BASE7_LOW 17
|
||||
#define FRACDIV_BASE7_HIGH 22
|
||||
#define FRACDIV_BASE7_FDIV0W 13
|
||||
|
||||
#define FRACDIV_BASE8_CNT 0
|
||||
#define FRACDIV_BASE9_CNT 0
|
||||
|
||||
#define FRACDIV_BASE10_CNT 1
|
||||
#define FRACDIV_BASE10_LOW 23
|
||||
#define FRACDIV_BASE10_HIGH 23
|
||||
#define FRACDIV_BASE10_FDIV0W 8
|
||||
|
||||
#define FRACDIV_BASE11_CNT 0
|
||||
|
||||
#define CGU_NDOMAINS 12
|
||||
#define CLKID_INVALIDCLK -1
|
||||
#define CLKID_INVALIDDOMAIN -1
|
||||
|
||||
/************************************************************************
|
||||
* Public Types
|
||||
************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* Clock domains */
|
||||
|
||||
enum lpc313x_domainid_e
|
||||
{
|
||||
DOMAINID_SYS = 0, /* Domain 0: SYS_BASE */
|
||||
DOMAINID_AHB0APB0, /* Domain 1: AHB0APB0_BASE */
|
||||
DOMAINID_AHB0APB1, /* Domain 2: AHB0APB1_BASE */
|
||||
DOMAINID_AHB0APB2, /* Domain 3: AHB0APB2_BASE */
|
||||
DOMAINID_AHB0APB3, /* Domain 4: AHB0APB3_BASE */
|
||||
DOMAINID_PCM, /* Domain 5: PCM_BASE */
|
||||
DOMAINID_UART, /* Domain 6: UART_BASE */
|
||||
DOMAINID_CLK1024FS, /* Domain 7: CLK1024FS_BASE */
|
||||
DOMAINID_BCK0, /* Domain 8: BCK0_BASE */
|
||||
DOMAINID_BCK1, /* Domain 9: BCK1_BASE */
|
||||
DOMAINID_SPI, /* Domain 10: SPI_BASE */
|
||||
DOMAINID_SYSCLKO /* Domain 11: SYSCLKO_BASE */
|
||||
};
|
||||
|
||||
/* Clock IDs -- These are indices must correspond to the register
|
||||
* offsets in lpc313x_cgu.h
|
||||
*/
|
||||
|
||||
enum lpc313x_clockid_e
|
||||
{
|
||||
/* Domain 0: SYS_BASE */
|
||||
|
||||
CLKID_APB0CLK = 0, /* 0 APB0_CLK */
|
||||
CLKID_SBAPB1CLK, /* 1 APB1_CLK */
|
||||
CLKID_APB2CLK, /* 2 APB2_CLK */
|
||||
CLKID_APB3CLK, /* 3 APB3_CLK */
|
||||
CLKID_APB4CLK, /* 4 APB4_CLK */
|
||||
CLKID_AHB2INTCCLK, /* 5 AHB_TO_INTC_CLK */
|
||||
CLKID_AHB0CLK, /* 6 AHB0_CLK */
|
||||
CLKID_EBICLK, /* 7 EBI_CLK */
|
||||
CLKID_DMAPCLK, /* 8 DMA_PCLK */
|
||||
CLKID_DMACLKGATED, /* 9 DMA_CLK_GATED */
|
||||
CLKID_NANDFLASHS0CLK, /* 10 NANDFLASH_S0_CLK */
|
||||
CLKID_NANDFLASHECCCLK, /* 11 NANDFLASH_ECC_CLK */
|
||||
CLKID_NANDFLASHAESCLK, /* 12 NANDFLASH_AES_CLK (Reserved on LPC313x) */
|
||||
CLKID_NANDFLASHNANDCLK, /* 13 NANDFLASH_NAND_CLK */
|
||||
CLKID_NANDFLASHPCLK, /* 14 NANDFLASH_PCLK */
|
||||
CLKID_CLOCKOUT, /* 15 CLOCK_OUT */
|
||||
CLKID_ARM926CORECLK, /* 16 ARM926_CORE_CLK */
|
||||
CLKID_ARM926BUSIFCLK, /* 17 ARM926_BUSIF_CLK */
|
||||
CLKID_ARM926RETIMECLK, /* 18 ARM926_RETIME_CLK */
|
||||
CLKID_SDMMCHCLK, /* 19 SD_MMC_HCLK */
|
||||
CLKID_SDMMCCCLKIN, /* 20 SD_MMC_CCLK_IN */
|
||||
CLKID_USBOTGAHBCLK, /* 21 USB_OTG_AHB_CLK */
|
||||
CLKID_ISRAM0CLK, /* 22 ISRAM0_CLK */
|
||||
CLKID_REDCTLRSCLK, /* 23 RED_CTL_RSCLK */
|
||||
CLKID_ISRAM1CLK, /* 24 ISRAM1_CLK (LPC313x only) */
|
||||
CLKID_ISROMCLK, /* 25 ISROM_CLK */
|
||||
CLKID_MPMCCFGCLK, /* 26 MPMC_CFG_CLK */
|
||||
CLKID_MPMCCFGCLK2, /* 27 MPMC_CFG_CLK2 */
|
||||
CLKID_MPMCCFGCLK3, /* 28 MPMC_CFG_CLK3 */
|
||||
CLKID_INTCCLK, /* 29 INTC_CLK */
|
||||
|
||||
/* Domain 1: AHB0APB0BASE */
|
||||
|
||||
CLKID_AHB2APB0PCLK, /* 30 AHB_TO_APB0_PCLK */
|
||||
CLKID_EVENTROUTERPCLK, /* 31 EVENT_ROUTER_PCLK */
|
||||
CLKID_ADCPCLK, /* 32 ADC_PCLK */
|
||||
CLKID_ADCCLK, /* 33 ADC_CLK */
|
||||
CLKID_WDOGPCLK, /* 34 WDOG_PCLK */
|
||||
CLKID_IOCONFPCLK, /* 35 IOCONF_PCLK */
|
||||
CLKID_CGUPCLK, /* 36 CGU_PCLK */
|
||||
CLKID_SYSCREGPCLK, /* 37 SYSCREG_PCLK */
|
||||
CLKID_OTPPCLK, /* 38 OTP_PCLK (Reserved on LPC313X) */
|
||||
CLKID_RNGPCLK, /* 39 RNG_PCLK */
|
||||
|
||||
/* Domain 2: AHB0APB1BASE */
|
||||
|
||||
CLKID_AHB2APB1PCLK, /* 40 AHB_TO_APB1_PCLK */
|
||||
CLKID_TIMER0PCLK, /* 41 TIMER0_PCLK */
|
||||
CLKID_TIMER1PCLK, /* 42 TIMER1_PCLK */
|
||||
CLKID_TIMER2PCLK, /* 43 TIMER2_PCLK */
|
||||
CLKID_TIMER3PCLK, /* 44 TIMER3_PCLK */
|
||||
CLKID_PWMPCLK, /* 45 PWM_PCLK */
|
||||
CLKID_PWMPCLKREGS, /* 46 PWM_PCLK_REGS */
|
||||
CLKID_PWMCLK, /* 47 PWM_CLK */
|
||||
CLKID_I2C0PCLK, /* 48 I2C0_PCLK */
|
||||
CLKID_I2C1PCLK, /* 49 I2C1_PCLK */
|
||||
|
||||
/* Domain 3: AHB0APB2BASE */
|
||||
|
||||
CLKID_AHB2APB2PCLK, /* 50 AHB_TO_APB2_PCLK */
|
||||
CLKID_PCMPCLK, /* 51 PCM_PCLK */
|
||||
CLKID_PCMAPBPCLK, /* 52 PCM_APB_PCLK */
|
||||
CLKID_UARTAPBCLK, /* 53 UART_APB_CLK */
|
||||
CLKID_LCDPCLK, /* 54 LCD_PCLK */
|
||||
CLKID_LCDCLK, /* 55 LCD_CLK */
|
||||
CLKID_SPIPCLK, /* 56 SPI_PCLK */
|
||||
CLKID_SPIPCLKGATED, /* 57 SPI_PCLK_GATED */
|
||||
|
||||
/* Domain 4: AHB0APB3BASE */
|
||||
CLKID_AHB2APB3PCLK, /* 58 AHB_TO_APB3_PCLK */
|
||||
CLKID_I2SCFGPCLK, /* 59 I2S_CFG_PCLK */
|
||||
CLKID_EDGEDETPCLK, /* 60 EDGE_DET_PCLK */
|
||||
CLKID_I2STXFIFO0PCLK, /* 61 I2STX_FIFO_0_PCLK */
|
||||
CLKID_I2STXIF0PCLK, /* 62 I2STX_IF_0_PCLK */
|
||||
CLKID_I2STXFIFO1PCLK, /* 63 I2STX_FIFO_1_PCLK */
|
||||
CLKID_I2STXIF1PCLK, /* 64 I2STX_IF_1_PCLK */
|
||||
CLKID_I2SRXFIFO0PCLK, /* 65 I2SRX_FIFO_0_PCLK */
|
||||
CLKID_I2SRXIF0PCLK, /* 66 I2SRX_IF_0_PCLK */
|
||||
CLKID_I2SRXFIFO1PCLK, /* 67 I2SRX_FIFO_1_PCLK */
|
||||
CLKID_I2SRXIF1PCLK, /* 68 I2SRX_IF_1_PCLK */
|
||||
CLKID_RESERVED69, /* 69 Reserved */
|
||||
CLKID_RESERVED70, /* 70 Reserved */
|
||||
|
||||
/* Domain 5: PCM_BASE */
|
||||
|
||||
CLKID_PCMCLKIP, /* 71 PCM_CLK_IP */
|
||||
|
||||
/* Domain 6: UART_BASE */
|
||||
|
||||
CLKID_UARTUCLK, /* 72 UART_U_CLK */
|
||||
|
||||
/* Domain 7: CLK1024FS_BASE */
|
||||
|
||||
CLKID_I2SEDGEDETECTCLK, /* 73 I2S_EDGE_DETECT_CLK */
|
||||
CLKID_I2STXBCK0N, /* 74 I2STX_BCK0_N */
|
||||
CLKID_I2STXWS0, /* 75 I2STX_WS0 */
|
||||
CLKID_I2STXCLK0, /* 76 I2STX_CLK0 */
|
||||
CLKID_I2STXBCK1N, /* 77 I2STX_BCK1_N */
|
||||
CLKID_I2STXWS1, /* 78 I2STX_WS1 */
|
||||
CLKID_CLK256FS, /* 79 CLK_256FS */
|
||||
CLKID_I2SRXBCK0N, /* 80 I2SRX_BCK0_N */
|
||||
CLKID_I2SRXWS0, /* 81 I2SRX_WS0 */
|
||||
CLKID_I2SRXBCK1N, /* 82 I2SRX_BCK1_N */
|
||||
CLKID_I2SRXWS1, /* 83 I2SRX_WS1 */
|
||||
CLKID_RESERVED84, /* 84 Reserved */
|
||||
CLKID_RESERVED85, /* 85 Reserved */
|
||||
CLKID_RESERVED86, /* 86 Reserved */
|
||||
|
||||
/* Domain 8: BCK0_BASE */
|
||||
|
||||
CLKID_I2SRXBCK0, /* 87 I2SRX_BCK0 */
|
||||
|
||||
/* Domain 9: BCK1_BASE */
|
||||
|
||||
CLKID_I2SRXBCK1, /* 88 I2SRX_BCK1 */
|
||||
|
||||
/* Domain 10: SPI_BASE */
|
||||
|
||||
CLKID_SPICLK, /* 89 SPI_CLK */
|
||||
CLKID_SPICLKGATED, /* 90 SPI_CLK_GATED */
|
||||
|
||||
/* Domain 11: SYSCLKO_BASE */
|
||||
|
||||
CLKID_SYSCLKO /* 91 SYSCLK_O */
|
||||
};
|
||||
|
||||
/************************************************************************
|
||||
* Public Data
|
||||
************************************************************************/
|
||||
|
||||
/************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************/
|
||||
|
||||
/* Enable the specified clock */
|
||||
|
||||
static inline void lpc313x_enableclock(enum lpc313x_clockid_e clkid)
|
||||
{
|
||||
uint32_t address = LPC313X_CGU_PCR((int)clkid);
|
||||
uint32_t regval = getreg32(address);
|
||||
|
||||
regval |= CGU_PCR_RUN;
|
||||
putreg32(regval, address);
|
||||
}
|
||||
|
||||
/* Disable the specified clock */
|
||||
|
||||
static inline void lpc313x_disableclock(enum lpc313x_clockid_e clkid)
|
||||
{
|
||||
uint32_t address = LPC313X_CGU_PCR((int)clkid);
|
||||
uint32_t regval = getreg32(address);
|
||||
|
||||
regval &= ~CGU_PCR_RUN;
|
||||
putreg32(regval, address);
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************/
|
||||
|
||||
/************************************************************************
|
||||
* Name: lpc313x_clkdomain
|
||||
*
|
||||
* Description:
|
||||
* Given a clock ID, return the ID of the domain in which the clock
|
||||
* resides.
|
||||
************************************************************************/
|
||||
|
||||
EXTERN enum lpc313x_domainid_e lpc313x_clkdomain(enum lpc313x_clockid_e clkid);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_LPC313X_CGUDRVR_H */
|
||||
124
arch/arm/src/lpc313x/lpc313x_clkdomain.c
Executable file
124
arch/arm/src/lpc313x/lpc313x_clkdomain.c
Executable file
@ -0,0 +1,124 @@
|
||||
/************************************************************************
|
||||
* arch/arm/src/lpc313x/lpc313x_clkdomain.c
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* References:
|
||||
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
|
||||
* - lpc313x.cdl.drivers.zip example driver code
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************/
|
||||
|
||||
/************************************************************************
|
||||
* Included Files
|
||||
************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "lpc313x_cgudrvr.h"
|
||||
|
||||
/************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************/
|
||||
|
||||
/************************************************************************
|
||||
* Private Data
|
||||
************************************************************************/
|
||||
|
||||
/************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************/
|
||||
|
||||
/************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************/
|
||||
|
||||
/************************************************************************
|
||||
* Name: lpc313x_clkdomain
|
||||
*
|
||||
* Description:
|
||||
* Given a clock ID, return the ID of the domain in which the clock
|
||||
* resides.
|
||||
************************************************************************/
|
||||
|
||||
enum lpc313x_domainid_e lpc313x_clkdomain(enum lpc313x_clockid_e clkid)
|
||||
{
|
||||
if (clkid <= CLKID_SYSBASE_LAST) /* Domain 0: SYS_BASE */
|
||||
{
|
||||
return DOMAINID_SYS;
|
||||
}
|
||||
else if (clkid <= CLKID_AHB0APB0_LAST) /* Domain 1: AHB0APB0_BASE */
|
||||
{
|
||||
return DOMAINID_AHB0APB0;
|
||||
}
|
||||
else if (clkid <= CLKID_AHB0APB1_LAST) /* Domain 2: AHB0APB1_BASE */
|
||||
{
|
||||
return DOMAINID_AHB0APB1;
|
||||
}
|
||||
else if (clkid <= CLKID_AHB0APB2_LAST) /* Domain 3: AHB0APB2_BASE */
|
||||
{
|
||||
return DOMAINID_AHB0APB2;
|
||||
}
|
||||
else if (clkid <= CLKID_AHB0APB3_LAST) /* Domain 4: AHB0APB3_BASE */
|
||||
{
|
||||
return DOMAINID_AHB0APB3;
|
||||
}
|
||||
else if (clkid <= CLKID_PCM_LAST) /* Domain 5: PCM_BASE */
|
||||
{
|
||||
return DOMAINID_PCM;
|
||||
}
|
||||
else if (clkid <= CLKID_UART_LAST) /* Domain 6: UART_BASE */
|
||||
{
|
||||
return DOMAINID_UART;
|
||||
}
|
||||
else if (clkid <= CLKID_CLK1024FS_LAST) /* Domain 7: CLK1024FS_BASE */
|
||||
{
|
||||
return DOMAINID_CLK1024FS;
|
||||
}
|
||||
else if (clkid <= CLKID_I2SRXBCK0_LAST) /* Domain 8: BCK0_BASE */
|
||||
{
|
||||
return DOMAINID_BCK0;
|
||||
}
|
||||
else if (clkid <= CLKID_I2SRXBCK1_LAST) /* Domain 9: BCK1_BASE */
|
||||
{
|
||||
return DOMAINID_BCK1;
|
||||
}
|
||||
else if (clkid <= CLKID_SPI_LAST) /* Domain 10: SPI_BASE */
|
||||
{
|
||||
return DOMAINID_SPI;
|
||||
}
|
||||
else /* if (clkid <= CLKID_SYSCLKO_LAST) */ /* Domain 11: SYSCLKO_BASE */
|
||||
{
|
||||
return DOMAINID_SYSCLKO;
|
||||
}
|
||||
}
|
||||
@ -47,12 +47,13 @@
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "arm.h"
|
||||
#include "up_arch.h"
|
||||
#include "os_internal.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "lpc313x_intc.h"
|
||||
#include "lpc313x_cgu.h"
|
||||
#include "lpc313x_cgudrvr.h"
|
||||
#include "lpc313x_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
@ -115,6 +116,16 @@ void up_irqinitialize(void)
|
||||
INTC_REQUEST_PRIOLEVEL(1)|INTC_REQUEST_WEPRIO, address);
|
||||
|
||||
}
|
||||
|
||||
/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
current_regs = NULL;
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
irqrestore(SVC_MODE | PSR_F_BIT);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@ -97,7 +97,7 @@
|
||||
*/
|
||||
|
||||
#define TIMER_CTRL_ENABLE (1 << 7) /* Bit 7: Timer enable */
|
||||
#define TIMER_CTRL_MODE (1 << 6) /* Bit 6: Periodic timer mode */
|
||||
#define TIMER_CTRL_PERIODIC (1 << 6) /* Bit 6: Periodic timer mode */
|
||||
#define TIMER_CTRL_PRESCALE_SHIFT (2) /* Bits 2-3: Timer pre-scale */
|
||||
#define TIMER_CTRL_PRESCALE_MASK (3 << TIMER_CTRL_PRESCALE_SHIFT)
|
||||
# define TIMER_CTRL_PRESCALE_DIV1 (0 << TIMER_CTRL_PRESCALE_SHIFT) /* Divider=1 Stages=0 */
|
||||
|
||||
@ -44,6 +44,7 @@
|
||||
#include <nuttx/config.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
# include "lpc313x_cgudrvr.h"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@ -51,6 +52,26 @@
|
||||
************************************************************************************/
|
||||
|
||||
/* Clocking *************************************************************************/
|
||||
/* The following 3 bitsets determine which clocks will be enabled at initialization
|
||||
* time.
|
||||
*/
|
||||
|
||||
#define BOARD_CLKS_0_31 \
|
||||
(_RBIT(CLKID_APB0CLK,0)|_RBIT(CLKID_APB1CLK,0)|_RBIT(CLKID_APB2CLK,0)|\
|
||||
_RBIT(CLKID_APB3CLK,0)|_RBIT(CLKID_APB4CLK,0)|_RBIT(CLKID_AHB2INTCCLK,0)|\
|
||||
_RBIT(CLKID_AHB0CLK,0)|_RBIT(CLKID_ARM926CORECLK,0)|_RBIT(CLKID_ARM926BUSIFCLK,0)|\
|
||||
_RBIT(CLKID_ARM926RETIMECLK,0)|_RBIT(CLKID_ISRAM0CLK,0)|_RBIT(CLKID_ISRAM1CLK,0)|\
|
||||
_RBIT(CLKID_ISROMCLK,0)|_RBIT(CLKID_INTCCLK,0)|_RBIT(CLKID_AHB2APB0ASYNCPCLK,0)|\
|
||||
_RBIT(CLKID_EVENTROUTERPCLK,0)|_RBIT(CLKID_CLOCKOUT,0))
|
||||
|
||||
#define BOARD_CLKS_32_63 \
|
||||
(_RBIT(CLKID_IOCONFPCLK,32)|_RBIT(CLKID_CGUPCLK,32)|_RBIT(CLKID_SYSCREGPCLK,32)|\
|
||||
_RBIT(CLKID_OTPPCLK,32)|_RBIT(CLKID_AHB2APB1ASYNCPCLK,32)|_RBIT(CLKID_AHB2APB2ASYNCPCLK,32)|\
|
||||
_RBIT(CLKID_AHB2APB3ASYNCPCLK,32)|_RBIT(CLKID_EDGEDETPCLK,32))
|
||||
|
||||
#define BOARD_CLKS_64_92 \
|
||||
(0)
|
||||
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user