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NSH link management now works! The last fix was to the Ethernet drivers: They cannot disable clocking to the Ethernet blok on ifdown. Otherwise, we cannot communicate with the PHY

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This commit is contained in:
Gregory Nutt 2014-08-17 17:54:46 -06:00
parent 754541a381
commit 96e1bf0ec2
4 changed files with 97 additions and 0 deletions
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25
arch/arm/src/sam34/sam_emac.c
View File

@ -2842,6 +2842,29 @@ static void sam_rxreset(struct sam_emac_s *priv)
static void sam_emac_reset(struct sam_emac_s *priv)
{
#ifdef CONFIG_NETDEV_PHY_IOCTL
uint32_t regval;
/* We are supporting PHY IOCTLs, then do not reset the MAC. If we do,
* then we cannot communicate with the PHY. So, instead, just disable
* interrupts, cancel timers, and disable TX and RX.
*/
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
/* Reset RX and TX logic */
sam_rxreset(priv);
sam_txreset(priv);
/* Disable Rx and Tx, plus the statistics registers. */
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~(EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
sam_putreg(priv, SAM_EMAC_NCR, regval);
#else
/* Disable all EMAC interrupts */
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
@ -2858,6 +2881,8 @@ static void sam_emac_reset(struct sam_emac_s *priv)
/* Disable clocking to the EMAC peripheral */
sam_emac_disableclk();
#endif
}
/****************************************************************************

22
arch/arm/src/sama5/sam_emaca.c
View File

@ -2892,6 +2892,26 @@ static void sam_rxreset(struct sam_emac_s *priv)
static void sam_emac_reset(struct sam_emac_s *priv)
{
#ifdef CONFIG_NETDEV_PHY_IOCTL
/* We are supporting PHY IOCTLs, then do not reset the MAC. If we do,
* then we cannot communicate with the PHY. So, instead, just disable
* interrupts, cancel timers, and disable TX and RX.
*/
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
/* Reset RX and TX logic */
sam_rxreset(priv);
sam_txreset(priv);
/* Disable Rx and Tx, plus the statistics registers. */
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~(EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
sam_putreg(priv, SAM_EMAC_NCR, regval);
#else
/* Disable all EMAC interrupts */
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
@ -2908,6 +2928,8 @@ static void sam_emac_reset(struct sam_emac_s *priv)
/* Disable clocking to the EMAC peripheral */
sam_emac_disableclk();
#endif
}
/****************************************************************************

28
arch/arm/src/sama5/sam_emacb.c
View File

@ -524,7 +524,9 @@ static int sam_phyinit(struct sam_emac_s *priv);
static void sam_txreset(struct sam_emac_s *priv);
static void sam_rxreset(struct sam_emac_s *priv);
static void sam_emac_enableclk(struct sam_emac_s *priv);
#ifndef CONFIG_NETDEV_PHY_IOCTL
static void sam_emac_disableclk(struct sam_emac_s *priv);
#endif
static void sam_emac_reset(struct sam_emac_s *priv);
static void sam_macaddress(struct sam_emac_s *priv);
static int sam_emac_configure(struct sam_emac_s *priv);
@ -3498,6 +3500,7 @@ static void sam_emac_enableclk(struct sam_emac_s *priv)
*
****************************************************************************/
#ifndef CONFIG_NETDEV_PHY_IOCTL
static void sam_emac_disableclk(struct sam_emac_s *priv)
{
#if defined(CONFIG_SAMA5_EMAC0) && defined(CONFIG_SAMA5_EMAC1)
@ -3523,6 +3526,7 @@ static void sam_emac_disableclk(struct sam_emac_s *priv)
sam_emac1_disableclk();
#endif
}
#endif
/****************************************************************************
* Function: sam_emac_reset
@ -3542,6 +3546,28 @@ static void sam_emac_disableclk(struct sam_emac_s *priv)
static void sam_emac_reset(struct sam_emac_s *priv)
{
#ifdef CONFIG_NETDEV_PHY_IOCTL
uint32_t regval;
/* We are supporting PHY IOCTLs, then do not reset the MAC. If we do,
* then we cannot communicate with the PHY. So, instead, just disable
* interrupts, cancel timers, and disable TX and RX.
*/
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_ALL);
/* Reset RX and TX logic */
sam_rxreset(priv);
sam_txreset(priv);
/* Disable Rx and Tx, plus the statistics registers. */
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
regval &= ~(EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
#else
/* Disable all EMAC interrupts */
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_ALL);
@ -3558,6 +3584,8 @@ static void sam_emac_reset(struct sam_emac_s *priv)
/* Disable clocking to the EMAC peripheral */
sam_emac_disableclk(priv);
#endif
}
/****************************************************************************

22
arch/arm/src/sama5/sam_gmac.c
View File

@ -2940,6 +2940,26 @@ static void sam_rxreset(struct sam_gmac_s *priv)
static void sam_gmac_reset(struct sam_gmac_s *priv)
{
#ifdef CONFIG_NETDEV_PHY_IOCTL
/* We are supporting PHY IOCTLs, then do not reset the MAC. If we do,
* then we cannot communicate with the PHY. So, instead, just disable
* interrupts, cancel timers, and disable TX and RX.
*/
sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_ALL);
/* Reset RX and TX logic */
sam_rxreset(priv);
sam_txreset(priv);
/* Disable Rx and Tx, plus the statistics registers. */
regval = sam_getreg(priv, SAM_GMAC_NCR);
regval &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN | GMAC_NCR_WESTAT);
sam_putreg(priv, SAM_GMAC_NCR, regval);
#else
/* Disable all GMAC interrupts */
sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_ALL);
@ -2956,6 +2976,8 @@ static void sam_gmac_reset(struct sam_gmac_s *priv)
/* Disable clocking to the GMAC peripheral */
sam_gmac_disableclk();
#endif
}
/****************************************************************************