diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c
index 747fd08d33..0e65511e56 100644
--- a/arch/arm/src/sam34/sam_emac.c
+++ b/arch/arm/src/sam34/sam_emac.c
@@ -2842,6 +2842,29 @@ static void sam_rxreset(struct sam_emac_s *priv)
 
 static void sam_emac_reset(struct sam_emac_s *priv)
 {
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+  uint32_t regval;
+
+  /* We are supporting PHY IOCTLs, then do not reset the MAC.  If we do,
+   * then we cannot communicate with the PHY.  So, instead, just disable
+   * interrupts, cancel timers, and disable TX and RX.
+   */
+
+  sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
+
+  /* Reset RX and TX logic */
+
+  sam_rxreset(priv);
+  sam_txreset(priv);
+
+  /* Disable Rx and Tx, plus the statistics registers. */
+
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
+  regval &= ~(EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
+
+#else
+
   /* Disable all EMAC interrupts */
 
   sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
@@ -2858,6 +2881,8 @@ static void sam_emac_reset(struct sam_emac_s *priv)
   /* Disable clocking to the EMAC peripheral */
 
   sam_emac_disableclk();
+
+#endif
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c
index 701b3464e7..3dfc0d07e2 100644
--- a/arch/arm/src/sama5/sam_emaca.c
+++ b/arch/arm/src/sama5/sam_emaca.c
@@ -2892,6 +2892,26 @@ static void sam_rxreset(struct sam_emac_s *priv)
 
 static void sam_emac_reset(struct sam_emac_s *priv)
 {
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+  /* We are supporting PHY IOCTLs, then do not reset the MAC.  If we do,
+   * then we cannot communicate with the PHY.  So, instead, just disable
+   * interrupts, cancel timers, and disable TX and RX.
+   */
+
+  sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
+
+  /* Reset RX and TX logic */
+
+  sam_rxreset(priv);
+  sam_txreset(priv);
+
+  /* Disable Rx and Tx, plus the statistics registers. */
+
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
+  regval &= ~(EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
+
+#else
   /* Disable all EMAC interrupts */
 
   sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
@@ -2908,6 +2928,8 @@ static void sam_emac_reset(struct sam_emac_s *priv)
   /* Disable clocking to the EMAC peripheral */
 
   sam_emac_disableclk();
+
+#endif
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c
index a149ccba0f..905eb1a5d3 100644
--- a/arch/arm/src/sama5/sam_emacb.c
+++ b/arch/arm/src/sama5/sam_emacb.c
@@ -524,7 +524,9 @@ static int  sam_phyinit(struct sam_emac_s *priv);
 static void sam_txreset(struct sam_emac_s *priv);
 static void sam_rxreset(struct sam_emac_s *priv);
 static void sam_emac_enableclk(struct sam_emac_s *priv);
+#ifndef CONFIG_NETDEV_PHY_IOCTL
 static void sam_emac_disableclk(struct sam_emac_s *priv);
+#endif
 static void sam_emac_reset(struct sam_emac_s *priv);
 static void sam_macaddress(struct sam_emac_s *priv);
 static int  sam_emac_configure(struct sam_emac_s *priv);
@@ -3498,6 +3500,7 @@ static void sam_emac_enableclk(struct sam_emac_s *priv)
  *
  ****************************************************************************/
 
+#ifndef CONFIG_NETDEV_PHY_IOCTL
 static void sam_emac_disableclk(struct sam_emac_s *priv)
 {
 #if defined(CONFIG_SAMA5_EMAC0) && defined(CONFIG_SAMA5_EMAC1)
@@ -3523,6 +3526,7 @@ static void sam_emac_disableclk(struct sam_emac_s *priv)
   sam_emac1_disableclk();
 #endif
 }
+#endif
 
 /****************************************************************************
  * Function: sam_emac_reset
@@ -3542,6 +3546,28 @@ static void sam_emac_disableclk(struct sam_emac_s *priv)
 
 static void sam_emac_reset(struct sam_emac_s *priv)
 {
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+  uint32_t regval;
+
+  /* We are supporting PHY IOCTLs, then do not reset the MAC.  If we do,
+   * then we cannot communicate with the PHY.  So, instead, just disable
+   * interrupts, cancel timers, and disable TX and RX.
+   */
+
+  sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_ALL);
+
+  /* Reset RX and TX logic */
+
+  sam_rxreset(priv);
+  sam_txreset(priv);
+
+  /* Disable Rx and Tx, plus the statistics registers. */
+
+  regval  = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
+  regval &= ~(EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
+  sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
+
+#else
   /* Disable all EMAC interrupts */
 
   sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_ALL);
@@ -3558,6 +3584,8 @@ static void sam_emac_reset(struct sam_emac_s *priv)
   /* Disable clocking to the EMAC peripheral */
 
   sam_emac_disableclk(priv);
+
+#endif
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c
index dc78bb7c26..89a47ff80d 100644
--- a/arch/arm/src/sama5/sam_gmac.c
+++ b/arch/arm/src/sama5/sam_gmac.c
@@ -2940,6 +2940,26 @@ static void sam_rxreset(struct sam_gmac_s *priv)
 
 static void sam_gmac_reset(struct sam_gmac_s *priv)
 {
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+  /* We are supporting PHY IOCTLs, then do not reset the MAC.  If we do,
+   * then we cannot communicate with the PHY.  So, instead, just disable
+   * interrupts, cancel timers, and disable TX and RX.
+   */
+
+  sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_ALL);
+
+  /* Reset RX and TX logic */
+
+  sam_rxreset(priv);
+  sam_txreset(priv);
+
+  /* Disable Rx and Tx, plus the statistics registers. */
+
+  regval  = sam_getreg(priv, SAM_GMAC_NCR);
+  regval &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN | GMAC_NCR_WESTAT);
+  sam_putreg(priv, SAM_GMAC_NCR, regval);
+
+#else
   /* Disable all GMAC interrupts */
 
   sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_ALL);
@@ -2956,6 +2976,8 @@ static void sam_gmac_reset(struct sam_gmac_s *priv)
   /* Disable clocking to the GMAC peripheral */
 
   sam_gmac_disableclk();
+
+#endif
 }
 
 /****************************************************************************