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xtensa/esp32s3: Fix alignment of FPU registers in exception context

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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei 2022-08-24 17:38:05 -03:00 committed by Xiang Xiao
parent 1014c3e795
commit 96f77cb6a6
1 changed files with 9 additions and 10 deletions
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19
arch/xtensa/include/irq.h
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@ -68,6 +68,10 @@
* Pre-processor Definitions
****************************************************************************/
#ifndef ALIGN_UP
# define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
#endif
/* IRQ Stack Frame Format. Each value is a uint32_t register index */
#define REG_PC (0) /* Return PC */
@ -138,18 +142,13 @@
#endif
#if XCHAL_CP_NUM > 0
# if (XCHAL_TOTAL_SA_ALIGN == 8) && ((_REG_CP_START & 1) == 1)
/* Fpu first address must align to cp align size. */
/* FPU first address must align to CP align size. */
# define REG_CP_DUMMY (_REG_CP_START + 0)
# define XCPTCONTEXT_REGS (_REG_CP_START + 1)
# else
# define XCPTCONTEXT_REGS _REG_CP_START
# endif
# define XCPTCONTEXT_SIZE ((4 * XCPTCONTEXT_REGS) + XTENSA_CP_SA_SIZE + 0x20)
# define XCPTCONTEXT_REGS ALIGN_UP(_REG_CP_START, XCHAL_TOTAL_SA_ALIGN / 4)
# define XCPTCONTEXT_SIZE ((4 * XCPTCONTEXT_REGS) + XTENSA_CP_SA_SIZE + 0x20)
#else
# define XCPTCONTEXT_REGS _REG_CP_START
# define XCPTCONTEXT_SIZE ((4 * XCPTCONTEXT_REGS) + 0x20)
# define XCPTCONTEXT_REGS _REG_CP_START
# define XCPTCONTEXT_SIZE ((4 * XCPTCONTEXT_REGS) + 0x20)
#endif
/****************************************************************************