SAMV7 QSPI: Add framework for a QSPI driver. Initial commit is just the SPI driver with some name changes

arch/arm/src/samv7/Make.defs

@@ -132,6 +132,10 @@ ifeq ($(CONFIG_SAMV7_SPI_SLAVE),y)
 CHIP_CSRCS += sam_spi_slave.c
 endif
 
+ifeq ($(CONFIG_SAMV7_QSPI),y)
+CHIP_CSRCS += sam_qspi.c
+endif
+
 ifeq ($(CONFIG_SAMV7_TWIHS0),y)
 CHIP_CSRCS += sam_twihs.c
 else ifeq ($(CONFIG_SAMV7_TWIHS1),y)

arch/arm/src/samv7/chip/sam_qspi.h

@@ -51,7 +51,12 @@
 /****************************************************************************************
  * Pre-processor Definitions
  ****************************************************************************************/
-/* QSPI register offsets *****************************************************************/
+/* General Characteristics **************************************************************/
+
+#define SAM_QSPI_MINBITS           8      /* Minimum word width */
+#define SAM_QSPI_MAXBITS           16     /* Maximum word width */
+
+/* QSPI register offsets ****************************************************************/
 
 #define SAM_QSPI_CR_OFFSET         0x0000 /* Control Register */
 #define SAM_QSPI_MR_OFFSET         0x0004 /* Mode Register */
@@ -73,7 +78,7 @@
 #define SAM_QSPI_WPSR_OFFSET       0x00e8 /* Write Protection Status Register */
                                          /* 0xec-0xfc: Reserved */
 
-/* QSPI register addresses ***************************************************************/
+/* QSPI register addresses **************************************************************/
 
 #define SAM_QSPI0_CR               (SAM_QSPI0_BASE+SAM_QSPI_CR_OFFSET)   /* Control Register */
 #define SAM_QSPI0_MR               (SAM_QSPI0_BASE+SAM_QSPI_MR_OFFSET)   /* Mode Register */
@@ -111,7 +116,7 @@
 #  define SAM_QSPI1_WPSR           (SAM_QSPI1_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */
 #endif
 
-/* QSPI register bit definitions *********************************************************/
+/* QSPI register bit definitions ********************************************************/
 
 /* QSPI Control Register */
 
@@ -132,7 +137,7 @@
 #  define QSPI_MR_CSMODE_SYSTEM    (2 << QSPI_MR_PCS_SHIFT) /* CS deasserted after each transfer */
 #define QSPI_MR_NBBITS_SHIFT       (8)       /* Bits 8-11: Number Of Bits Per Transfer */
 #define QSPI_MR_NBBITS_MASK        (15 << QSPI_MR_NBBITS_SHIFT)
-#  define QSPI_MR_NBBITS(n)        ((uint32_t)((n)-8) << QSPI_MR_NBBITS_SHIFT)
+#  define QSPI_MR_NBBITS(n)        ((uint32_t)((n)-SAM_QSPI_MINBITS) << QSPI_MR_NBBITS_SHIFT)
 #  define QSPI_MR_NBBITS_8BIT      (0 << QSPI_MR_NBBITS_SHIFT) /* 8 bits for transfer */
 #  define QSPI_MR_NBBITS_9BIT      (1 << QSPI_MR_NBBITS_SHIFT) /* 9 bits for transfer */
 #  define QSPI_MR_NBBITS_10BIT     (2 << QSPI_MR_NBBITS_SHIFT) /* 10 bits for transfer */
@@ -176,8 +181,6 @@
 
 /* Serial Clock Register */
 
-#define QSPI_SCR_
-
 #define QSPI_SCR_CPOL              (1 << 0)  /* Bit 0:  Clock Polarity */
 #define QSPI_SCR_NCPHA             (1 << 1)  /* Bit 1:  Clock Phase */
 #define QSPI_SCR_SCBR_SHIFT        (8)       /* Bits 8-15: Serial Clock Baud Rate */

arch/arm/src/samv7/sam_qspi.h

@@ -0,0 +1,107 @@
+/****************************************************************************
+ * arch/arm/src/samv7/sam_qspi.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMV7_SAM_QSPI_H
+#define __ARCH_ARM_SRC_SAMV7_SAM_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "chip.h"
+#include "sam_config.h"
+
+#ifdef CONFIG_SAMV7_QSPI
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_qspi_initialize
+ *
+ * Description:
+ *   Initialize the selected QSPI port in master mode
+ *
+ * Input Parameter:
+ *   intf - Interface number(must be zero)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct spi_dev_s *sam_qspi_initialize(int intf);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_SAMV7_QSPI */
+#endif /* __ARCH_ARM_SRC_SAMV7_SAM_QSPI_H */