arch: imx6: Apply the latest imxrt/imxrt_enet.c to imx6/imx_enet.c
Summary: - Since imx_enet.c is based on imxrt_enet.c and still under debugging, the differences should be minimum to keep tracking the changes Impact: - None Testing: - Tested with sabre-6quad:netnsh with QEMU Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
Masayuki Ishikawa
Xiang Xiao
parent
0f2b774dec
commit
977367ce04
@ -24,6 +24,7 @@
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#include <nuttx/config.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <unistd.h>
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@ -108,6 +109,27 @@
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#define NENET_NBUFFERS \
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(CONFIG_IMX_ENET_NTXBUFFERS + CONFIG_IMX_ENET_NRXBUFFERS)
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/* Normally you would clean the cache after writing new values to the DMA
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* memory so assure that the dirty cache lines are flushed to memory
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* before the DMA occurs. And you would invalid the cache after a data is
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* received via DMA so that you fetch the actual content of the data from
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* the cache.
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*
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* These conditions are not fully supported here. If the write-throuch
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* D-Cache is enabled, however, then many of these issues go away: The
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* cache clean operation does nothing (because there are not dirty cache
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* lines) and the cache invalid operation is innocuous (because there are
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* never dirty cache lines to be lost; valid data will always be reloaded).
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*
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* At present, we simply insist that write through cache be enabled.
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*/
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#if 0
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#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
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# error Write back D-Cache not yet supported
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#endif
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#endif
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/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
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* second.
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*/
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@ -155,6 +177,11 @@
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* 7. BOARD_PHY_ISDUPLEX: A macro that can convert the status register
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* value into a boolean: true=duplex mode, false=half-duplex mode
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*
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* The imxrt1050-evk board uses a KSZ8081 PHY
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* The Versiboard2 uses a LAN8720 PHY
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* The Teensy-4.1 board uses a DP83825I PHY
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*
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* ...and further PHY descriptions here.
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*/
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/* TODO:
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@ -180,6 +207,15 @@
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# define BOARD_PHY_10BASET(s) (((s)&MII_LAN8720_SPSCR_10MBPS) != 0)
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# define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0)
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# define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0)
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#elif defined(CONFIG_ETH0_PHY_DP83825I)
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# define BOARD_PHY_NAME "DP83825I"
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# define BOARD_PHYID1 MII_PHYID1_DP83825I
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# define BOARD_PHYID2 MII_PHYID2_DP83825I
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# define BOARD_PHY_STATUS MII_DP83825I_PHYSTS
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# define BOARD_PHY_ADDR (0)
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# define BOARD_PHY_10BASET(s) (((s) & MII_DP83825I_PHYSTS_SPEED) != 0)
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# define BOARD_PHY_100BASET(s) (((s) & MII_DP83825I_PHYSTS_SPEED) == 0)
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# define BOARD_PHY_ISDUPLEX(s) (((s) & MII_DP83825I_PHYSTS_DUPLEX) != 0)
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#else
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# error "Unrecognized or missing PHY selection"
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#endif
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@ -361,6 +397,52 @@ static void imx_reset(struct imx_driver_s *priv);
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Function: imx_swap16/32
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*
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* Description:
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* The descriptors are represented by structures Unfortunately, when the
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* structures are overlaid on the data, the bytes are reversed because
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* the underlying hardware writes the data in big-endian byte order.
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*
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* Input Parameters:
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* value - The value to be byte swapped
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*
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* Returned Value:
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* The byte swapped value
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*
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****************************************************************************/
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#if 0 /* Use builtins if the compiler supports them */
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#ifndef CONFIG_ENDIAN_BIG
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static inline uint32_t imx_swap32(uint32_t value)
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{
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uint32_t result = 0;
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__asm__ __volatile__
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(
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"rev %0, %1"
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:"=r" (result)
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: "r"(value)
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);
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return result;
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}
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static inline uint16_t imx_swap16(uint16_t value)
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{
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uint16_t result = 0;
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__asm__ __volatile__
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(
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"revsh %0, %1"
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:"=r" (result)
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: "r"(value)
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);
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return result;
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}
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#endif
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#endif
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/****************************************************************************
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* Function: imx_txringfull
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*
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@ -615,7 +697,7 @@ static inline void imx_dispatch(FAR struct imx_driver_s *priv)
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NETDEV_RXPACKETS(&priv->dev);
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#ifdef CONFIG_NET_PKT
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/* When packet sockets are enabled, feed the frame into the packet tap */
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/* When packet sockets are enabled, feed the frame into the tap */
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pkt_input(&priv->dev);
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#endif
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@ -636,7 +718,7 @@ static inline void imx_dispatch(FAR struct imx_driver_s *priv)
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ipv4_input(&priv->dev);
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/* If the above function invocation resulted in data that should be
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* sent out on the network, the field d_len will set to a value > 0.
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* sent out on the network, d_len field will set to a value > 0.
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*/
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if (priv->dev.d_len > 0)
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@ -668,7 +750,7 @@ static inline void imx_dispatch(FAR struct imx_driver_s *priv)
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if (BUF->type == HTONS(ETHTYPE_IP6))
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{
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ninfo("Iv6 frame\n");
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ninfo("IPv6 frame\n");
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NETDEV_RXIPV6(&priv->dev);
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/* Give the IPv6 packet to the network layer */
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@ -676,7 +758,7 @@ static inline void imx_dispatch(FAR struct imx_driver_s *priv)
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ipv6_input(&priv->dev);
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/* If the above function invocation resulted in data that should be
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* sent out on the network, the field d_len will set to a value > 0.
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* sent out on the network, d_len field will set to a value > 0.
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*/
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if (priv->dev.d_len > 0)
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@ -945,7 +1027,7 @@ static void imx_enet_interrupt_work(FAR void *arg)
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NETDEV_ERRORS(&priv->dev);
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nerr("ERROR: Network interface error occurred (0x%08X)\n",
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nerr("ERROR: Network interface error occurred (0x%08" PRIX32 ")\n",
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(pending & ERROR_INTERRUPTS));
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}
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@ -1020,7 +1102,7 @@ static void imx_enet_interrupt_work(FAR void *arg)
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* Function: imx_enet_interrupt
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*
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* Description:
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* Three interrupt sources will vector this this function:
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* Three interrupt sources will vector to this function:
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* 1. Ethernet MAC transmit interrupt handler
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* 2. Ethernet MAC receive interrupt handler
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* 3.
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@ -1101,8 +1183,7 @@ static void imx_txtimeout_work(FAR void *arg)
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* The last TX never completed. Reset the hardware and start again.
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*
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* Input Parameters:
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* argc - The number of available arguments
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* arg - The first argument
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* arg - The argument
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*
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* Returned Value:
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* None
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@ -1181,8 +1262,7 @@ static void imx_poll_work(FAR void *arg)
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* Periodic timer handler. Called from the timer interrupt handler.
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*
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* Input Parameters:
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* argc - The number of available arguments
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* arg - The first argument
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* arg - The argument
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*
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* Returned Value:
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* None
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@ -1231,10 +1311,10 @@ static int imx_ifup_action(struct net_driver_s *dev, bool resetphy)
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int ret;
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ninfo("Bringing up: %d.%d.%d.%d\n",
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(int)dev->d_ipaddr & 0xff,
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(int)(dev->d_ipaddr >> 8) & 0xff,
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(int)(dev->d_ipaddr >> 16) & 0xff,
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(int)dev->d_ipaddr >> 24);
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(int)(dev->d_ipaddr & 0xff),
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(int)((dev->d_ipaddr >> 8) & 0xff),
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(int)((dev->d_ipaddr >> 16) & 0xff),
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(int)(dev->d_ipaddr >> 24));
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/* Initialize ENET buffers */
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@ -2086,6 +2166,13 @@ static inline int imx_initphy(struct imx_driver_s *priv, bool renogphy)
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imx_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2,
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(phydata | (1 << 4)));
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imx_writemii(priv, phyaddr, MII_ADVERTISE,
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MII_ADVERTISE_100BASETXFULL |
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MII_ADVERTISE_100BASETXHALF |
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MII_ADVERTISE_10BASETXFULL |
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MII_ADVERTISE_10BASETXHALF |
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MII_ADVERTISE_CSMA);
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#elif defined (CONFIG_ETH0_PHY_LAN8720)
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/* Make sure that PHY comes up in correct mode when it's reset */
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@ -2096,6 +2183,25 @@ static inline int imx_initphy(struct imx_driver_s *priv, bool renogphy)
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/* ...and reset PHY */
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imx_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
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#elif defined (CONFIG_ETH0_PHY_DP83825I)
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/* Reset PHY */
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imx_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
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/* Set RMII mode and Indicate 50MHz clock */
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imx_writemii(priv, phyaddr, MII_DP83825I_RCSR,
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MII_DP83825I_RCSC_ELAST_2 | MII_DP83825I_RCSC_RMIICS);
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imx_writemii(priv, phyaddr, MII_ADVERTISE,
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MII_ADVERTISE_100BASETXFULL |
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MII_ADVERTISE_100BASETXHALF |
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MII_ADVERTISE_10BASETXFULL |
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MII_ADVERTISE_10BASETXHALF |
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MII_ADVERTISE_CSMA);
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#endif
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/* Start auto negotiation */
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