sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add beginning of m9s12x GPIO support

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3317 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-02-25 23:05:37 +00:00
parent 807c807b6b
commit 97806609b4
11 changed files with 949 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/src/lpc17xx/lpc17_irq.c
View File

@ -326,8 +326,6 @@ void up_irqinitialize(void)
lpc17_dumpnvic("initial", LPC17_IRQ_NIRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Initialize FIQs */
#ifdef CONFIG_ARCH_FIQ
@ -344,6 +342,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
setbasepri(NVIC_SYSH_PRIORITY_MAX);
irqrestore(0);
#endif

12
arch/hc/src/m9s12/Make.defs
View File

@ -43,5 +43,13 @@ CMN_CSRCS = up_allocateheap.c up_blocktask.c up_copystate.c up_createstack.c \
up_udelay.c up_unblocktask.c up_usestack.c
CHIP_ASRCS = m9s12_start.S m9s12_lowputc.S m9s12_saveusercontext.S
CHIP_CSRCS = m9s12_assert.c m9s12_serial.c m9s12_initialstate.c m9s12_irq.c \
m9s12_timerisr.c
CHIP_CSRCS = m9s12_assert.c m9s12_gpio.c m9s12_initialstate.c m9s12_irq.c \
m9s12_serial.c m9s12_timerisr.c
ifeq ($(CONFIG_GPIO_IRQ),y)
CHIP_CSRCS += m9s12_gpioint.c
endif
ifeq ($(CONFIG_DEBUG_GPIO),y)
CHIP_CSRCS += m9s12_gpiodbg.c
endif

84
arch/hc/src/m9s12/m9s12_dumpgpio.c Executable file
View File

@ -0,0 +1,84 @@
/****************************************************************************
* arch/arm/src/m9s12/m9s12_dumpgpio.c
* arch/arm/src/chip/m9s12_dumpgpio.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "m9s12_internal.h"
#ifdef CONFIG_DEBUG_GPIO
/****************************************************************************
* Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/************************************************************************************
* Function: hcs12_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the base address of the provided pinset.
*
************************************************************************************/
int hcs12_dumpgpio(uint16_t pinset, const char *msg)
{
#warning "Not implemented"
return -ENOSYS;
}
#endif /* CONFIG_DEBUG_GPIO */

438
arch/hc/src/m9s12/m9s12_gpio.c Executable file
View File

@ -0,0 +1,438 @@
/****************************************************************************
* arch/arm/src/m9s12/m9s12_gpio.c
* arch/arm/src/chip/m9s12_gpio.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include "up_arch.h"
#include "m9s12_internal.h"
#include "m9s12_pim.h"
#include "m9s12_mebi.h"
/****************************************************************************
* Definitions
****************************************************************************/
/* GPIO management macros:
*
* The GPIO configuration is represented by a 16-bit value encoded as follows:
*
* xxII OUUR DMGG GPPP
* || |||| ||| `-Pin number
* || |||| || `- Port number
* || |||| | `- PIM Ports
* || |||| `- Direction
* || |||`- Reduced drive
* || ||`- Polarity
* || |`- Pull up (or down)
* || `- Wired OR open drain
* |`- Interrupt or rising/falling (polarity)
* `- Interrupt
*
* NOTE: MEBI ports E and K can have special configurations as controlled by
* the PEAR and MODE registers. Those special configurations are not managed
* by the logic below; that logic is only intended to support general GPIO
* pin usage.
*/
/* PIM ports (T,S,G,H,J,L) */
#define HCS12_PIM_NPORTS 6
/* MEBI ports (A,B,E,K) */
#define HCS12_MEBI_NPORTS 4
/* Which ports have which registers? */
#define HCS12_PORT_T (1 << 0)
#define HCS12_PORT_S (1 << 1)
#define HCS12_PORT_G (1 << 2)
#define HCS12_PORT_H (1 << 3)
#define HCS12_PORT_J (1 << 4)
#define HCS12_PORT_L (1 << 5)
#define HCS12_PORT_ALL 0x3f
#define HCS12_IO_PORTS HCS12_PORT_ALL
#define HCS12_INPUT_PORTS HCS12_PORT_ALL
#define HCS12_DDR_PORTS HCS12_PORT_ALL
#define HCS12_RDR_PORTS HCS12_PORT_ALL
#define HCS12_PER_PORTS HCS12_PORT_ALL
#define HCS12_PS_PORTS HCS12_PORT_ALL
#define HCS12_WOM_PORTS (HCS12_PORT_S|HCS12_PORT_L)
#define HCS12_IE_PORTS (HCS12_PORT_G|HCS12_PORT_H|HCS12_PORT_J)
#define HCS12_IF_PORTS (HCS12_PORT_G|HCS12_PORT_H|HCS12_PORT_J)
/* Decoding help macros */
#define HCS12_PIN(cfg) (((cfg) & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT)
#define HCS12_PORTNDX(cfg) (((cfg) >> GPIO_PORT_SHIFT) & 7)
#define HCS12_PIMPORT(cfg) (((cfg) & GPIO_PORT_PIM) != 0)
#define HCS12_MEBIPORT(cfg) (((cfg) & GPIO_PORT_PIM) == 0)
#define HCS12_PULL(cfg) (((cfg) & GPIO_PULLUP_MASK) >> GPIO_PULLUP_SHIFT)
# define HCS12_PULL_NONE 0
# define HCS12_PULL_POLARITY 1
# define HCS12_PULL_ENABLE 2
# define HCS12_PULL_UP 2
# define HCS12_PULL_DOWN 3
#define HCS12_INTERRUPT(cfg) (((cfg) & GPIO_INT_MASK) >> GPIO_INT_SHIFT)
# define HCS12_INT_NONE 0
# define HCS12_INT_POLARITY 1
# define HCS12_INT_ENABLE 2
# define HCS12_INT_FALLING 2
# define HCS12_INT_RISING 3
/****************************************************************************
* Private Types
****************************************************************************/
struct mebi_portaddr_s
{
uint16_t data; /* Data register */
uint16_t ddr; /* Direction register */
};
/****************************************************************************
* Public Data
****************************************************************************/
static const struct mebi_portaddr_s mebi_portaddr[HCS12_MEBI_NPORTS] =
{
{HCS12_MEBI_PORTA, HCS12_MEBI_DDRA}, /* Port A */
{HCS12_MEBI_PORTB, HCS12_MEBI_DDRB}, /* Port B */
{HCS12_MEBI_PORTE, HCS12_MEBI_DDRE}, /* Port E */
{HCS12_MEBI_PORTK, HCS12_MEBI_DDRK} /* Port K */
};
static uint8_t mebi_bits[HCS12_MEBI_NPORTS] =
{
(1 << 0), (1 << 1), (1 << 4), (1 << 7)
};
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Misc. Low-Level, Inline Helper Functions
****************************************************************************/
static inline void gpio_writebit(uint16_t regaddr, uint8_t pin, bool set)
{
uint8_t regval = getreg8(regaddr);
if (set)
{
regval |= (1 << pin);
}
else
{
regval &= ~(1 << pin);
}
putreg8(regval, regaddr);
}
static inline bool gpio_readbit(uint16_t regaddr, uint8_t pin)
{
uint8_t regval = getreg8(regaddr);
return ((regval & (1 << pin)) != 0);
}
static inline void pim_direction(uint8_t portndx, uint8_t pin, bool output)
{
gpio_writebit(HCS12_PIM_PORT_DDR(portndx), pin, output);
}
static inline void mebi_direction(uint8_t portndx, uint8_t pin, bool output)
{
gpio_writebit(mebi_portaddr[portndx].ddr, pin, output);
}
static inline void pim_opendrain(uint8_t portndx, uint8_t pin, bool opendrain)
{
DEBUGASSERT(!opendrain || (HCS12_WOM_PORTS & (1 << pin)) != 0);
gpio_writebit(HCS12_PIM_PORT_WOM(portndx), pin, opendrain);
}
static inline void pim_pullpin(uint8_t portndx, uint8_t pin, uint8_t pull)
{
bool enable = false;
bool polarity = false;
if ((pull & HCS12_PULL_ENABLE) != 0)
{
enable = true;
if ((pull & HCS12_PULL_POLARITY) != 0)
{
polarity = true;
}
}
gpio_writebit(HCS12_PIM_PORT_PER(portndx), pin, enable);
gpio_writebit(HCS12_PIM_PORT_PS(portndx), pin, polarity);
}
static inline void mebi_pullport(uint8_t portndx, uint8_t pull)
{
uint8_t regval = getreg8(HCS12_MEBI_PUCR);
if (pull == HCS12_PULL_UP)
{
regval |= mebi_bits[portndx];
}
else
{
regval &= ~mebi_bits[portndx];
}
putreg8(regval, HCS12_MEBI_PUCR);
}
static inline void pim_rdpin(uint8_t portndx, uint8_t pin, bool rdenable)
{
gpio_writebit(HCS12_PIM_PORT_RDR(portndx), pin, rdenable);
}
static inline void mebi_rdport(uint8_t portndx, bool rdenable)
{
uint8_t regval = getreg8(HCS12_MEBI_RDRIV);
if (rdenable)
{
regval |= mebi_bits[portndx];
}
else
{
regval &= ~mebi_bits[portndx];
}
putreg8(regval, HCS12_MEBI_RDRIV);
}
static inline void pim_interrupt(uint8_t portndx, unsigned pin, uint8_t type)
{
if (type != HCS12_INT_NONE)
{
DEBUGASSERT((HCS12_IE_PORTS & (1 << pin)) != 0);
gpio_writebit(HCS12_PIM_PORT_IE(portndx), pin, false);
gpio_writebit(HCS12_PIM_PORT_PS(portndx), pin, ((type & GPIO_INT_POLARITY) != 0));
}
else if ((HCS12_IE_PORTS & (1 << pin)) != 0)
{
gpio_writebit(HCS12_PIM_PORT_IE(portndx), pin, false);
}
}
/****************************************************************************
* Name: pim_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
static inline void pim_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin)
{
/* Sanity checking -- Check if the pin will be enabled as an interrupt
* (later)
*/
DEBUGASSERT(portndx < HCS12_PIM_NPORTS);
#ifdef CONFIG_DEBUG
if ((cfgset) & GPIO_INT_ENABLE) != 0)
{
/* Yes.. then it must not be tagged as an output */
ASSERT(((cfgset) & GPIO_DIRECTION) != GPIO_OUTPUT);
/* If the pull-driver is also enabled, it must be enabled with a
* compatible priority.
*/
if ((cfgset) & GPIO_PULL_ENABLE) != 0)
{
if ((cfgset) & GPIO_INT_POLARITY) != 0)
{
ASSERT(((cfgset) & GPIO_PULL_POLARITY) != 0);
}
else
{
ASSERT(((cfgset) & GPIO_PULL_POLARITY) = 0);
}
}
}
#endif
pim_direction(portndx, pin, (((cfgset) & GPIO_DIRECTION) == GPIO_OUTPUT));
pim_opendrain(portndx, pin, (((cfgset) & GPIO_OPENDRAN) != 0));
pim_pullpin(portndx, pin, HCS12_PULL(cfgset));
pim_rdpin(portndx, pin, (((cfgset) & GPIO_REDUCED) != 0));
pim_interrupt(portndx, pin, HCS12_INTERRUPT(cfgset));
}
/****************************************************************************
* Name: mebi_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
static inline void mebi_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin)
{
DEBUGASSERT(portndx < HCS12_MEBI_NPORTS);
mebi_direction(portndx, pin, (((cfgset) & GPIO_DIRECTION) == GPIO_OUTPUT));
mebi_pullport(portndx, HCS12_PULL(cfgset));
mebi_rdport(portndx, (((cfgset) & GPIO_REDUCED) != 0));
}
/****************************************************************************
* Read/Write Helpers
****************************************************************************/
static inline void pim_gpiowrite(uint8_t portndx, uint8_t pin, bool value)
{
uint16_t regaddr = HCS12_PIM_PORT_IO(portndx)
DEBUGASSERT(portndx < HCS12_PIM_NPORTS);
gpio_writebit(regaddr, pin, value);
}
static inline void mebi_gpiowrite(uint8_t portndx, uint8_t pin, bool value)
{
uint16_t regaddr;
DEBUGASSERT(portndx < HCS12_MEBI_NPORTS);
regaddr = mebi_portaddr[portndx].data;
gpio_writebit(regaddr, pin, value);
}
static inline bool pim_gpioread(uint8_t portndx, uint8_t pin)
{
uint16_t regaddr = HCS12_PIM_PORT_INPUT(portndx)
DEBUGASSERT(portndx < HCS12_PIM_NPORTS);
return gpio_readbit(regaddr, pin);
}
static inline bool mebi_gpioread(uint8_t portndx, uint8_t pin)
{
uint16_t regaddr;
DEBUGASSERT(portndx < HCS12_MEBI_NPORTS);
regaddr = mebi_portaddr[portndx].data;
return gpio_readbit(regaddr, pin);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: hcs12_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
int hcs12_configgpio(uint16_t cfgset)
{
uint8_t portndx = HCS12_PORTNDX(cfgset);
uint8_t pin = HCS12_PIN(cfgset);
if (HCS12_PIMPORT(cfgset))
{
pim_configgpio(cfgset, portndx, pin);
}
else
{
mebi_configgpio(cfgset, portndx, pin);
}
return OK;
}
/****************************************************************************
* Name: hcs12_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void hcs12_gpiowrite(uint16_t pinset, bool value)
{
uint8_t portndx = HCS12_PORTNDX(pinset);
uint8_t pin = HCS12_PIN(pinset);
DEBUGASSERT((pinset & GPIO_DIRECTION) == GPIO_OUTPUT);
if (HCS12_PIMPORT(pinset))
{
pim_gpiowrite(portndx, pin, value);
}
else
{
mebi_gpiowrite(portndx, pin, value);
}
}
/****************************************************************************
* Name: hcs12_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool hcs12_gpioread(uint16_t pinset)
{
uint8_t portndx = HCS12_PORTNDX(pinset);
uint8_t pin = HCS12_PIN(pinset);
if (HCS12_PIMPORT(pinset))
{
return pim_gpioread(portndx, pin);
}
else
{
return mebi_gpioread(portndx, pin);
}
}

108
arch/hc/src/m9s12/m9s12_gpioirq.c Executable file
View File

@ -0,0 +1,108 @@
/****************************************************************************
* arch/arm/src/m9s12/m9s12_gpioirq.c
* arch/arm/src/chip/m9s12_gpioirq.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "m9s12_internal.h"
#ifdef CONFIG_GPIO_IRQ
/****************************************************************************
* Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: hcs12_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
void hcs12_gpioirqinitialize(void)
{
#warning "Not implemented"
}
/****************************************************************************
* Name: hcs12_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
****************************************************************************/
void hcs12_gpioirqenable(int irq)
{
#warning "Not implemented"
}
/****************************************************************************
* Name: hcs12_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
void hcs12_gpioirqdisable(int irq)
{
#warning "Not implemented"
}
#endif /* CONFIG_GPIO_IRQ */

213
arch/hc/src/m9s12/m9s12_internal.h
View File

@ -55,7 +55,132 @@
* Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* GPIO management macros:
*
* The GPIO configuration is represented by a 16-bit value encoded as follows:
*
* xxII OUUR DMGG GPPP
* || |||| ||| `-Pin number
* || |||| || `- Port number
* || |||| | `- PIM Ports
* || |||| `- Direction
* || |||`- Reduced drive
* || ||`- Polarity
* || |`- Pull up (or down)
* || `- Wired OR open drain
* |`- Interrupt or rising/falling (polarity)
* `- Interrupt
*
* NOTE: MEBI ports E and K can have special configurations as controlled by
* the PEAR and MODE registers. Those special configurations are not managed
* by the logic below; that logic is only intended to support general GPIO
* pin usage.
*/
/* Interrupts:
*
* xxII xxxx xxxx xxxx
*
* For PIM ports G, H, and J. NOTE: If pull up/down is also selected, then
* it must be consistent with the selected interrupt edge (because both are
* controlled by the same polarity register):
*
* Rising edge <-> Pull down
* Falling Edge <-> Pull up
*
* Selecting input also selects direction == input (it is unless to specify
* GPIO_INPUT and an error if GPIO_OUTPUT is also specified)
*/
#define GPIO_INT_SHIFT (12)
#define GPIO_INT_MASK (3 << GPIO_PULLUP_SHIFT)
# define GPIO_INT_POLARITY (1 << GPIO_PULLUP_SHIFT)
# define GPIO_INT_ENABLE (2 << GPIO_PULLUP_SHIFT)
# define GPIO_INT_FALLING (2 << GPIO_PULLUP_SHIFT)
# define GPIO_INT_RISING (3 << GPIO_PULLUP_SHIFT)
/* Wired OR open-drain:
*
* xxxx Oxxx xxxx xxxx
*
* Only PIM ports S and L
*/
#define GPIO_OPENDRAN (1 << 11)
/* Pull up (or down):
*
* xxxx xUUx xxxx xxxx
*
* For PIM ports (T,S,G,H,J,L), selection is per-pin
* For MEBI ports (A,B,E,K), selection is per-port, polarity is ignored
*/
#define GPIO_PULLUP_SHIFT (9)
#define GPIO_PULLUP_MASK (3 << GPIO_PULLUP_SHIFT)
# define GPIO_PULL_POLARITY (1 << GPIO_PULLUP_SHIFT)
# define GPIO_PULL_ENABLE (2 << GPIO_PULLUP_SHIFT)
# define GPIO_PULLUP (2 << GPIO_PULLUP_SHIFT)
# define GPIO_PULLDOWN (3 << GPIO_PULLUP_SHIFT)
/* Reduced drive:
*
* xxxx xxxR xxxx xxxx
*
* For PIM ports (T,S,G,H,J,L), selection is per-pin
* For MEBI ports (A,B,E,K), selection is per-port
*/
#define GPIO_REDUCED (1 << 8)
/* Data direction (All ports -- A,B,E,K,T,S,G,H,J,L)
*
* xxxx xxxx Dxxx xxxx
*
*/
#define GPIO_DIRECTION (1 << 7)
# define GPIO_INPUT (0)
# define GPIO_OUTPUT GPIO_DIRECTION
/* Port selection
*
* xxxx xxxx xGGG Gxxx
*
* Ports A, B, E, and K reside in the MEBI block
* Ports T,S,G,H,J, and L reside in the PIM block.
*/
#define GPIO_PORT_SHIFT 3
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
# define GPIO_PORT_A (0 << GPIO_PORT_SHIFT)
# define GPIO_PORT_B (1 << GPIO_PORT_SHIFT)
# define GPIO_PORT_E (2 << GPIO_PORT_SHIFT)
# define GPIO_PORT_K (3 << GPIO_PORT_SHIFT)
# define GPIO_PORT_PIM (8 << GPIO_PORT_SHIFT)
# define GPIO_PORT_T (8 << GPIO_PORT_SHIFT)
# define GPIO_PORT_S (9 << GPIO_PORT_SHIFT
# define GPIO_PORT_G (10 << GPIO_PORT_SHIFT)
# define GPIO_PORT_H (11 << GPIO_PORT_SHIFT)
# define GPIO_PORT_J (12 << GPIO_PORT_SHIFT)
# define GPIO_PORT_L (13 << GPIO_PORT_SHIFT)
/* Pin numbers
*
* xxxx xxxx xxxx xPPP
*/
#define GPIO_PIN_SHIFT (0)
#define GPIO_PIN_MASK (7 << GPIO_PORT_SHIFT)
# define GPIO_PIN_0 (0 << GPIO_PORT_SHIFT)
# define GPIO_PIN_1 (1 << GPIO_PORT_SHIFT)
# define GPIO_PIN_2 (2 << GPIO_PORT_SHIFT)
# define GPIO_PIN_3 (3 << GPIO_PORT_SHIFT)
# define GPIO_PIN_4 (4 << GPIO_PORT_SHIFT)
# define GPIO_PIN_5 (5 << GPIO_PORT_SHIFT)
# define GPIO_PIN_6 (6 << GPIO_PORT_SHIFT)
# define GPIO_PIN_7 (7 << GPIO_PORT_SHIFT)
/************************************************************************************
* Inline Functions
@ -79,6 +204,92 @@ extern "C" {
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: hcs12_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for GPIO pins.
*
************************************************************************************/
#ifdef CONFIG_GPIO_IRQ
EXTERN void hcs12_gpioirqinitialize(void);
#else
# define hcs12_gpioirqinitialize()
#endif
/************************************************************************************
* Name: hcs12_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
************************************************************************************/
EXTERN int hcs12_configgpio(uint16_t cfgset);
/************************************************************************************
* Name: hcs12_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
************************************************************************************/
EXTERN void hcs12_gpiowrite(uint16_t pinset, bool value);
/************************************************************************************
* Name: hcs12_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
************************************************************************************/
EXTERN bool hcs12_gpioread(uint16_t pinset);
/************************************************************************************
* Name: hcs12_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
************************************************************************************/
#ifdef CONFIG_GPIO_IRQ
EXTERN void hcs12_gpioirqenable(int irq);
#else
# define hcs12_gpioirqenable(irq)
#endif
/************************************************************************************
* Name: hcs12_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
************************************************************************************/
#ifdef CONFIG_GPIO_IRQ
EXTERN void hcs12_gpioirqdisable(int irq);
#else
# define hcs12_gpioirqdisable(irq)
#endif
/************************************************************************************
* Function: hcs12_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the base address of the provided pinset.
*
************************************************************************************/
#ifdef CONFIG_DEBUG_GPIO
EXTERN int hcs12_dumpgpio(uint16_t pinset, const char *msg);
#else
# define hcs12_dumpgpio(p,m)
#endif
/************************************************************************************
* Function: hcs12_ethinitialize
*

14
arch/hc/src/m9s12/m9s12_irq.c
View File

@ -83,4 +83,18 @@ void up_irqinitialize(void)
/* currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL;
/* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*/
#ifdef CONFIG_GPIO_IRQ
lpc17_gpioirqinitialize();
#endif
/* And finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
irqrestore(0);
#endif
}

1
arch/hc/src/m9s12/m9s12_pim.h
View File

@ -98,6 +98,7 @@
#define HCS12_PIM_PORT_RDR(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_RDR_OFFSET)
#define HCS12_PIM_PORT_PER(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_PER_OFFSET)
#define HCS12_PIM_PORT_PS(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_PS_OFFSET)
#define HCS12_PIM_PORT_WOM(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_WOM_OFFSET)
#define HCS12_PIM_PORT_IE(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IE_OFFSET)
#define HCS12_PIM_PORT_IF(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IF_OFFSET)

71
configs/ne64badge/README.txt
View File

@ -110,6 +110,7 @@ PIN PIN NAME BOARD SIGNAL NOTES
44 RESET J3 RESET_L Also to SW3
57 BKGD/MODC/TAGHI_B BDM BKGD CON6A
85 PAD0 VR1 Potentiometer
86 PAD1 J3 ANALOG_IN0 Not used on board
87 PAD2 J3 ANALOG_IN1 " " " " "" " "
88 PAD3 J3 ANALOG_IN2 " " " " "" " "
@ -120,14 +121,8 @@ PIN PIN NAME BOARD SIGNAL NOTES
73 PHY_RXP J7 RD+ RJ45 connector
74 PHY_RXN J7 RD- RJ45 connector
51 PL6/TXER/KWL6 N/C N/C
52 PL5/TXDV/KWL5 N/C N/C
58 PL4/COLLED Collision LED red
59 PL3/DUPLED Full Duplex LED yellow
81 PL2/SPDLED 100Mbps Speed LED yellow
83 PL1/LNKLED Link Good LED green
84 PL0/ACTLED Activity LED yellow
Ports A,B,E,K managed by the MEBI block
---------------------------------------
60 PA0/ADDR8/DATA8 J3 ADDR_DATA8 Not used on board
61 PA1/ADDR9/DATA9 J3 ADDR_DATA9 " " " " "" " "
62 PA2/ADDR10/DATA10 J3 ADDR_DATA10 " " " " "" " "
@ -146,15 +141,6 @@ PIN PIN NAME BOARD SIGNAL NOTES
18 PB6/ADDR6/DATA6 J3 ADDR_DATA6 " " " " "" " "
19 PB7/ADDR7/DATA7 J3 ADDR_DATA7 " " " " "" " "
97 PK0/XADR14 N/C N/C
98 PK1/XADR15 N/C N/C
99 PK2/XADR16 N/C N/C
100 PK3/XADR17 N/C N/C
103 PK4/XADR18 N/C N/C
104 PK5/XADR19 N/C N/C
105 PK6/XCS_B J3 XCS Not used on board
106 PK7/ECS_B/ROMCTL J3 ECS " " " " "" " "
56 PE0/XIRQ_B BUTTON1 SW1
55 PE1/IRQ_B J3 IRQ Not used on board
54 PE2/R_W J3 RW " " " " "" " "
@ -164,27 +150,22 @@ PIN PIN NAME BOARD SIGNAL NOTES
39 PE6/IPIPE1/MODB J3 MODB " " " " "" " "
38 PE7/NOACC/XCLKS_B pulled low pulled low
97 PK0/XADR14 N/C N/C
98 PK1/XADR15 N/C N/C
99 PK2/XADR16 N/C N/C
100 PK3/XADR17 N/C N/C
103 PK4/XADR18 N/C N/C
104 PK5/XADR19 N/C N/C
105 PK6/XCS_B J3 XCS Not used on board
106 PK7/ECS_B/ROMCTL J3 ECS " " " " "" " "
Ports T,S,G,H,J,L managed by the PIM Block
------------------------------------------
110 PT4/IOC1_4 J3 GPIO8 Not used on board
109 PT5/IOC1_5 J3 GPIO9 " " " " "" " "
108 PT6/IOC1_6 J3 GPIO10 " " " " "" " "
107 PT7/IOC1_7 N/C N/C
22 PG0/RXD0/KWG0 J3 GPIO0 Not used on board
23 PG1/RXD1/KWG1 J3 GPIO1 " " " " "" " "
24 PG2/RXD2/KWG2 J3 GPIO2 " " " " "" " "
25 PG3/RXD3/KWG3 J3 GPIO3 " " " " "" " "
26 PG4/RXCLK/KWG4 J3 GPIO4 " " " " "" " "
27 PG5/RXDV/KWG5 J3 GPIO5 " " " " "" " "
28 PG6/RXER/KWG6 J3 GPIO6 " " " " "" " "
29 PG7/KWG7 J3 GPIO7 " " " " "" " "
8 PJ0/MDC/KWJ0 LED1 D21, red
9 PJ1/MDIO/KWJ1 LED2 D22, red
20 PJ2/CRS/KWJ2 J3 SPI_CS Not used on board
21 PJ3/COL/KWJ3 N/C
112 PJ6/SDA/KWJ6 J3 I2C_DATA Not used on board
111 PJ7/SCL/KWJ7 J3 I2C_CLOCK " " " " "" " "
30 PS0/RXD0 RS232_RX Eventually maps to J2 RXD
31 PS1/TXD0 RS232_TX Eventually maps to J2 TXD
32 PS2/RXD1 J3&J4 UART_RX Not used on board
@ -194,6 +175,15 @@ PIN PIN NAME BOARD SIGNAL NOTES
36 PS6/SCK J3 SPI_CLOCK " " " " "" " "
37 PS7/SS_B J3 SPI_SS " " " " "" " "
22 PG0/RXD0/KWG0 J3 GPIO0 Not used on board
23 PG1/RXD1/KWG1 J3 GPIO1 " " " " "" " "
24 PG2/RXD2/KWG2 J3 GPIO2 " " " " "" " "
25 PG3/RXD3/KWG3 J3 GPIO3 " " " " "" " "
26 PG4/RXCLK/KWG4 J3 GPIO4 " " " " "" " "
27 PG5/RXDV/KWG5 J3 GPIO5 " " " " "" " "
28 PG6/RXER/KWG6 J3 GPIO6 " " " " "" " "
29 PG7/KWG7 J3 GPIO7 " " " " "" " "
7 PH0/TXD0/KWH0 N/C N/C
6 PH1/TXD1/KWH1 N/C N/C
5 PH2/TXD2/KWH2 J4 XBEE_RESET Not used on board
@ -201,6 +191,21 @@ PIN PIN NAME BOARD SIGNAL NOTES
3 PH4/TXCLK/KWH4 BUTTON2 SW2
2 PH5/TXDV/KWH5 J5 XBEE_LOAD_H Not used on board
1 PH6/TXER/KWH6 J4 XBEE_LOAD_L Not used on board
8 PJ0/MDC/KWJ0 LED1 D21, red
9 PJ1/MDIO/KWJ1 LED2 D22, red
20 PJ2/CRS/KWJ2 J3 SPI_CS Not used on board
21 PJ3/COL/KWJ3 N/C
112 PJ6/SDA/KWJ6 J3 I2C_DATA Not used on board
111 PJ7/SCL/KWJ7 J3 I2C_CLOCK " " " " "" " "
51 PL6/TXER/KWL6 N/C N/C
52 PL5/TXDV/KWL5 N/C N/C
58 PL4/COLLED Collision LED red
59 PL3/DUPLED Full Duplex LED yellow
81 PL2/SPDLED 100Mbps Speed LED yellow
83 PL1/LNKLED Link Good LED green
84 PL0/ACTLED Activity LED yellow
Development Environment
^^^^^^^^^^^^^^^^^^^^^^^

10
configs/ne64badge/ostest/defconfig
View File

@ -105,13 +105,13 @@ CONFIG_ARCH_DMA=n
# contiguous address space in memory.
#
CONFIG_HCS12_SERIALMON=y
CONFIG_HCS12_SERIALMON=n
CONFIG_HCS12_NONBANKED=y
#
# CS12 Sub-system support
#
CONFIG_HCS12_SCI0=n
CONFIG_HCS12_SCI0=y
CONFIG_HCS12_SCI1=n
#
@ -128,10 +128,10 @@ CONFIG_HCS12_SCI1=n
# CONFIG_SCIn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
# CONFIG_SCIn_2STOP - Two stop bits
#
CONFIG_SCI0_SERIAL_CONSOLE=n
CONFIG_SCI0_SERIAL_CONSOLE=y
CONFIG_SCI0_TXBUFSIZE=32
CONFIG_SCI0_RXBUFSIZE=32
CONFIG_SCI0_BAUD=115200
CONFIG_SCI0_BAUD=38400
CONFIG_SCI0_BITS=8
CONFIG_SCI0_PARITY=0
CONFIG_SCI0_2STOP=0
@ -139,7 +139,7 @@ CONFIG_SCI0_2STOP=0
CONFIG_SCI1_SERIAL_CONSOLE=n
CONFIG_SCI1_TXBUFSIZE=32
CONFIG_SCI1_RXBUFSIZE=32
CONFIG_SCI1_BAUD=115200
CONFIG_SCI1_BAUD=38400
CONFIG_SCI1_BITS=8
CONFIG_SCI1_PARITY=0
CONFIG_SCI1_2STOP=0

71
configs/ne64badge/src/ne64badge_internal.h
View File

@ -54,6 +54,7 @@
* 44 RESET J3 RESET_L Also to SW3
* 57 BKGD/MODC/TAGHI_B BDM BKGD CON6A
*
* 85 PAD0 VR1 Potentiometer
* 86 PAD1 J3 ANALOG_IN0 Not used on board
* 87 PAD2 J3 ANALOG_IN1 " " " " "" " "
* 88 PAD3 J3 ANALOG_IN2 " " " " "" " "
@ -64,14 +65,8 @@
* 73 PHY_RXP J7 RD+ RJ45 connector
* 74 PHY_RXN J7 RD- RJ45 connector
*
* 51 PL6/TXER/KWL6 N/C N/C
* 52 PL5/TXDV/KWL5 N/C N/C
* 58 PL4/COLLED Collision LED red
* 59 PL3/DUPLED Full Duplex LED yellow
* 81 PL2/SPDLED 100Mbps Speed LED yellow
* 83 PL1/LNKLED Link Good LED green
* 84 PL0/ACTLED Activity LED yellow
*
* Ports A,B,E,K managed by the MEBI block
* ---------------------------------------
* 60 PA0/ADDR8/DATA8 J3 ADDR_DATA8 Not used on board
* 61 PA1/ADDR9/DATA9 J3 ADDR_DATA9 " " " " "" " "
* 62 PA2/ADDR10/DATA10 J3 ADDR_DATA10 " " " " "" " "
@ -90,15 +85,6 @@
* 18 PB6/ADDR6/DATA6 J3 ADDR_DATA6 " " " " "" " "
* 19 PB7/ADDR7/DATA7 J3 ADDR_DATA7 " " " " "" " "
*
* 97 PK0/XADR14 N/C N/C
* 98 PK1/XADR15 N/C N/C
* 99 PK2/XADR16 N/C N/C
* 100 PK3/XADR17 N/C N/C
* 103 PK4/XADR18 N/C N/C
* 104 PK5/XADR19 N/C N/C
* 105 PK6/XCS_B J3 XCS Not used on board
* 106 PK7/ECS_B/ROMCTL J3 ECS " " " " "" " "
*
* 56 PE0/XIRQ_B BUTTON1 SW1
* 55 PE1/IRQ_B J3 IRQ Not used on board
* 54 PE2/R_W J3 RW " " " " "" " "
@ -108,27 +94,22 @@
* 39 PE6/IPIPE1/MODB J3 MODB " " " " "" " "
* 38 PE7/NOACC/XCLKS_B pulled low pulled low
*
* 97 PK0/XADR14 N/C N/C
* 98 PK1/XADR15 N/C N/C
* 99 PK2/XADR16 N/C N/C
* 100 PK3/XADR17 N/C N/C
* 103 PK4/XADR18 N/C N/C
* 104 PK5/XADR19 N/C N/C
* 105 PK6/XCS_B J3 XCS Not used on board
* 106 PK7/ECS_B/ROMCTL J3 ECS " " " " "" " "
*
* Ports T,S,G,H,J,L managed by the PIM Block
* ------------------------------------------
* 110 PT4/IOC1_4 J3 GPIO8 Not used on board
* 109 PT5/IOC1_5 J3 GPIO9 " " " " "" " "
* 108 PT6/IOC1_6 J3 GPIO10 " " " " "" " "
* 107 PT7/IOC1_7 N/C N/C
*
* 22 PG0/RXD0/KWG0 J3 GPIO0 Not used on board
* 23 PG1/RXD1/KWG1 J3 GPIO1 " " " " "" " "
* 24 PG2/RXD2/KWG2 J3 GPIO2 " " " " "" " "
* 25 PG3/RXD3/KWG3 J3 GPIO3 " " " " "" " "
* 26 PG4/RXCLK/KWG4 J3 GPIO4 " " " " "" " "
* 27 PG5/RXDV/KWG5 J3 GPIO5 " " " " "" " "
* 28 PG6/RXER/KWG6 J3 GPIO6 " " " " "" " "
* 29 PG7/KWG7 J3 GPIO7 " " " " "" " "
*
* 8 PJ0/MDC/KWJ0 LED1 D21, red
* 9 PJ1/MDIO/KWJ1 LED2 D22, red
* 20 PJ2/CRS/KWJ2 J3 SPI_CS Not used on board
* 21 PJ3/COL/KWJ3 N/C
* 112 PJ6/SDA/KWJ6 J3 I2C_DATA Not used on board
* 111 PJ7/SCL/KWJ7 J3 I2C_CLOCK " " " " "" " "
*
* 30 PS0/RXD0 RS232_RX Eventually maps to J2 RXD
* 31 PS1/TXD0 RS232_TX Eventually maps to J2 TXD
* 32 PS2/RXD1 J3&J4 UART_RX Not used on board
@ -138,6 +119,15 @@
* 36 PS6/SCK J3 SPI_CLOCK " " " " "" " "
* 37 PS7/SS_B J3 SPI_SS " " " " "" " "
*
* 22 PG0/RXD0/KWG0 J3 GPIO0 Not used on board
* 23 PG1/RXD1/KWG1 J3 GPIO1 " " " " "" " "
* 24 PG2/RXD2/KWG2 J3 GPIO2 " " " " "" " "
* 25 PG3/RXD3/KWG3 J3 GPIO3 " " " " "" " "
* 26 PG4/RXCLK/KWG4 J3 GPIO4 " " " " "" " "
* 27 PG5/RXDV/KWG5 J3 GPIO5 " " " " "" " "
* 28 PG6/RXER/KWG6 J3 GPIO6 " " " " "" " "
* 29 PG7/KWG7 J3 GPIO7 " " " " "" " "
*
* 7 PH0/TXD0/KWH0 N/C N/C
* 6 PH1/TXD1/KWH1 N/C N/C
* 5 PH2/TXD2/KWH2 J4 XBEE_RESET Not used on board
@ -145,6 +135,21 @@
* 3 PH4/TXCLK/KWH4 BUTTON2 SW2
* 2 PH5/TXDV/KWH5 J5 XBEE_LOAD_H Not used on board
* 1 PH6/TXER/KWH6 J4 XBEE_LOAD_L Not used on board
*
* 8 PJ0/MDC/KWJ0 LED1 D21, red
* 9 PJ1/MDIO/KWJ1 LED2 D22, red
* 20 PJ2/CRS/KWJ2 J3 SPI_CS Not used on board
* 21 PJ3/COL/KWJ3 N/C
* 112 PJ6/SDA/KWJ6 J3 I2C_DATA Not used on board
* 111 PJ7/SCL/KWJ7 J3 I2C_CLOCK " " " " "" " "
*
* 51 PL6/TXER/KWL6 N/C N/C
* 52 PL5/TXDV/KWL5 N/C N/C
* 58 PL4/COLLED Collision LED red
* 59 PL3/DUPLED Full Duplex LED yellow
* 81 PL2/SPDLED 100Mbps Speed LED yellow
* 83 PL1/LNKLED Link Good LED green
* 84 PL0/ACTLED Activity LED yellow
*/
/************************************************************************************