SAMA5D4: Completes PMC modifications for the SAMA5D4
This commit is contained in:
Gregory Nutt
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979b732f3b
@ -2,7 +2,7 @@
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* arch/arm/src/sama5/chip/sam_pmc.h
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* Power Management Controller (PMC) for the SAMA5
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -88,9 +88,12 @@
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#define SAM_PMC_PCDR1_OFFSET 0x0104 /* Peripheral Clock Disable Register 1 */
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#define SAM_PMC_PCSR1_OFFSET 0x0108 /* Peripheral Clock Status Register 1 */
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#define SAM_PMC_PCR_OFFSET 0x010c /* Peripheral Control Register */
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#define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */
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/* PMC register adresses ********************************************************************/
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#ifdef ATSAMA5D3
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# define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */
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#endif
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/* PMC register addresses *******************************************************************/
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#define SAM_PMC_SCER (SAM_PMC_VBASE+SAM_PMC_SCER_OFFSET)
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#define SAM_PMC_SCDR (SAM_PMC_VBASE+SAM_PMC_SCDR_OFFSET)
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@ -120,7 +123,10 @@
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#define SAM_PMC_PCDR1 (SAM_PMC_VBASE+SAM_PMC_PCDR1_OFFSET)
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#define SAM_PMC_PCSR1 (SAM_PMC_VBASE+SAM_PMC_PCSR1_OFFSET)
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#define SAM_PMC_PCR (SAM_PMC_VBASE+SAM_PMC_PCR_OFFSET)
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#define SAM_PMC_OCR (SAM_PMC_VBASE+SAM_PMC_OCR_OFFSET)
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#ifdef ATSAMA5D3
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# define SAM_PMC_OCR (SAM_PMC_VBASE+SAM_PMC_OCR_OFFSET)
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#endif
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/* PMC register bit definitions *************************************************************/
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@ -128,7 +134,10 @@
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* Clock Status Register common bit-field definitions
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*/
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#define PMC_PCK (1 << 0) /* Bit 0: Processor Clock */
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#ifdef ATSAMA5D3
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# define PMC_PCK (1 << 0) /* Bit 0: Processor Clock */
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#endif
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#define PMC_DDRCK (1 << 2) /* Bit 2: DDR Clock */
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#define PMC_LCDCK (1 << 3) /* Bit 3: LCD2x Clock */
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#define PMC_SMDCK (1 << 4) /* Bit 4: SMD Clock */
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@ -191,33 +200,47 @@
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#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */
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#define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */
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#define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */
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#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */
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#define PMC_CKGR_MOR_MOSCXTST_MASK (0x1ff << PMC_CKGR_MOR_MOSCXTST_SHIFT)
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#ifdef ATSAMA5D3
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# define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */
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#endif
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#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-15: Main Crystal Oscillator Start-up Time */
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#define PMC_CKGR_MOR_MOSCXTST_MASK (0xff << PMC_CKGR_MOR_MOSCXTST_SHIFT)
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#define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */
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#define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT)
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# define PMC_CKGR_MOR_KEY (0x37 << PMC_CKGR_MOR_KEY_SHIFT)
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#define PMC_CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */
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#define PMC_CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */
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#ifdef ATSAMA5D4
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# define PMC_CKGR_MOR_XT32KFME (1 << 26) /* Bit 26: Slow Crystal Oscillator Frequency Monitoring Enable */
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#endif
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/* PMC Clock Generator Main Clock Frequency Register */
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#define PMC_CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */
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#define PMC_CKGR_MCFR_MAINF_MASK (0xffff << PMC_CKGR_MCFR_MAINF_SHIFT)
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# define PMC_CKGR_MCFR_MAINF(n) ((uint32_t)(n) << PMC_CKGR_MCFR_MAINF_SHIFT)
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#define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */
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#define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */
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/* PMC Clock Generator PLLA Register */
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#define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */
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#define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT)
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# define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */
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# define PMC_CKGR_PLLAR_DIV_BYPASS (1 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */
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# define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */
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#undef SAMA5_HAVE_PLLAR_DIV
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#ifdef ATSAMA5D3
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# define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */
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# define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT)
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# define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */
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# define PMC_CKGR_PLLAR_DIV_BYPASS (1 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */
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# define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */
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# define SAMA5_HAVE_PLLAR_DIV 1
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#endif
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#define PMC_CKGR_PLLAR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */
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#define PMC_CKGR_PLLAR_COUNT_MASK (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define PMC_CKGR_PLLAR_OUT_SHIFT (16) /* Bits 16-17: PLLA Clock Frequency Range */
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#define PMC_CKGR_PLLAR_OUT_MASK (3 << PMC_CKGR_PLLAR_OUT_SHIFT)
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#define PMC_CKGR_PLLAR_OUT_SHIFT (14) /* Bits 14-17: PLLA Clock Frequency Range */
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#define PMC_CKGR_PLLAR_OUT_MASK (15 << PMC_CKGR_PLLAR_OUT_SHIFT)
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# define PMC_CKGR_PLLAR_OUT (0 << PMC_CKGR_PLLAR_OUT_SHIFT) /* To be programmed to 0 */
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#define PMC_CKGR_PLLAR_MUL_SHIFT (18) /* Bits 18-24: PLLA Multiplier */
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#define PMC_CKGR_PLLAR_MUL_MASK (0x7f << PMC_CKGR_PLLAR_MUL_SHIFT)
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@ -248,6 +271,10 @@
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# define PMC_MCKR_MDIV_PCKDIV3 (3 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 3 */
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#define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */
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#ifdef ATSAMA5D4
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# define PMC_MCKR_H32MXDIV (1 << 24) /* Bit 24: AHB 32-bit Matrix Divisor */
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#endif
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/* USB Clock Register PMC_USB */
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#define PMC_USB_USBS (1 << 0) /* Bit 0: USB Input Clock Selection */
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@ -301,6 +328,10 @@
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#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */
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#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */
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#ifdef ATSAMA5D4
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# define PMC_SR_XT32KERR (1 << 21) /* Bit 21: Slow Crystal Oscillator Error Interrupt */
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#endif
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/* PMC Fault Output Clear Register */
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#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */
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@ -309,12 +340,16 @@
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#define PMC_PLLICPR_ICP_PLLA_SHIFT (0) /* Bits 0-1: Charge Pump Current PLLA */
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#define PMC_PLLICPR_ICP_PLLA_MASK (3 << PMC_PLLICPR_ICP_PLLA_SHIFT)
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# define PMC_PLLICPR_ICP_PLLA(n) ((uint32_t)(n) << PMC_PLLICPR_ICP_PLLA_SHIFT)
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#define PMC_PLLICPR_IPLL_PLLA_SHIFT (8) /* Bits 8-10: Engineering Configuration PLLA */
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#define PMC_PLLICPR_IPLL_PLLA_MASK (7 << PMC_PLLICPR_IPLL_PLLA_SHIFT)
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# define PMC_PLLICPR_IPLL_PLLA(n) ((uint32_t)(n) << PMC_PLLICPR_IPLL_PLLA_SHIFT)
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#define PMC_PLLICPR_ICP_PLLU_SHIFT (16) /* Bits 16-17: Charge Pump Current PLL UTMI */
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#define PMC_PLLICPR_ICP_PLLU_MASK (3 << PMC_PLLICPR_ICP_PLLU_SHIFT)
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# define PMC_PLLICPR_ICP_PLLU(n) ((uint32_t)(n) << PMC_PLLICPR_ICP_PLLU_SHIFT)
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#define PMC_PLLICPR_IVCO_PLLU_SHIFT (14) /* Bits 24-15: Voltage Control Output Current PLL UTMI */
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#define PMC_PLLICPR_IVCO_PLLU_MASK (3 << PMC_PLLICPR_IVCO_PLLU_SHIFT)
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# define PMC_PLLICPR_IVCO_PLLU(n) ((uint32_t)(n) << PMC_PLLICPR_IVCO_PLLU_SHIFT)
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/* PMC Write Protect Mode Register */
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@ -373,19 +408,26 @@
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#define PMC_PCR_PID_MASK (63 << PMC_PCR_PID_SHIFT)
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# define PMC_PCR_PID(n) ((n) << PMC_PCR_PID_SHIFT)
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#define PMC_PCR_CMD (1 << 12) /* Bit 12: Command */
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#define PMC_PCR_DIV_SHIFT (16) /* Bits 16-17: Divisor Value */
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#define PMC_PCR_DIV_MASK (3 << PMC_PCR_DIV_SHIFT)
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# define PMC_PCR_DIV1 (0 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */
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# define PMC_PCR_DIV2 (1 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */
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# define PMC_PCR_DIV4 (2 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */
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# define PMC_PCR_DIV8 (3 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/8 */
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#ifdef ATSAMA5D3
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# define PMC_PCR_DIV_SHIFT (16) /* Bits 16-17: Divisor Value */
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# define PMC_PCR_DIV_MASK (3 << PMC_PCR_DIV_SHIFT)
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# define PMC_PCR_DIV1 (0 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */
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# define PMC_PCR_DIV2 (1 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */
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# define PMC_PCR_DIV4 (2 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */
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# define PMC_PCR_DIV8 (3 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/8 */
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#endif
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#define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */
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#ifdef ATSAMA5D3
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/* Oscillator Calibration Register */
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#define PMC_OCR_CAL_SHIFT (0) /* Bits 0-6: 12 MHz RC Oscillator Calibration bits */
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#define PMC_OCR_CAL_MASK (0x7f << PMC_OCR_CAL_SHIFT)
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#define PMC_OCR_SEL (1 << 7) /* Bit 7: Selection of RC Oscillator Calibration bits */
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# define PMC_OCR_CAL_SHIFT (0) /* Bits 0-6: 12 MHz RC Oscillator Calibration bits */
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# define PMC_OCR_CAL_MASK (0x7f << PMC_OCR_CAL_SHIFT)
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# define PMC_OCR_CAL(n) ((uint32_t)(n) << PMC_OCR_CAL_SHIFT)
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# define PMC_OCR_SEL (1 << 7) /* Bit 7: Selection of RC Oscillator Calibration bits */
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#endif
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/********************************************************************************************
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* Public Types
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@ -224,9 +224,15 @@ static inline void __ramfunc__ sam_pllasetup(void)
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/* Configure PLLA */
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#ifdef SAMA5_HAVE_PLLAR_DIV
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regval = (BOARD_CKGR_PLLAR_DIV | BOARD_CKGR_PLLAR_COUNT |
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BOARD_CKGR_PLLAR_OUT | BOARD_CKGR_PLLAR_MUL |
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PMC_CKGR_PLLAR_ONE);
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#else
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regval = (BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_OUT |
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BOARD_CKGR_PLLAR_MUL | PMC_CKGR_PLLAR_ONE);
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#endif
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putreg32(regval, SAM_PMC_CKGR_PLLAR);
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/* Set the PLL Charge Pump Current Register to zero */
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@ -94,22 +94,28 @@
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uint32_t sam_pllack_frequency(uint32_t mainclk)
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{
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uint32_t regval;
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#ifdef SAMA5_HAVE_PLLAR_DIV
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uint32_t diva;
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#endif
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uint32_t mula;
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uint32_t pllack;
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/* Get the PLLA divider (DIVA) and multiplier (MULA) */
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/* Get the PLLA configuration. We will multiply (and possibly divide)
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* the Main Clock to get the PLLA output clock (PLLACK).
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*/
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regval = getreg32(SAM_PMC_CKGR_PLLAR);
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pllack = mainclk;
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/* DIVA = 0: Divider output is 0
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* DIVA = 1: Divider is bypassed
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* DIVA = 2-255: Divider output is the selected clock divided by DIVA
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#ifdef SAMA5_HAVE_PLLAR_DIV
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/* Get the PLLA divider (DIVA)
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*
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* DIVA = 0: Divider output is 0
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* DIVA = 1: Divider is bypassed
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* DIVA = 2-255: Divider output is the selected clock divided by DIVA
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*/
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diva = (regval & PMC_CKGR_PLLAR_DIV_MASK) >> PMC_CKGR_PLLAR_DIV_SHIFT;
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pllack = mainclk;
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if (diva > 1)
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{
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pllack /= diva;
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@ -118,10 +124,13 @@ uint32_t sam_pllack_frequency(uint32_t mainclk)
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{
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return 0;
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}
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#endif
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/* MULA = 0: PLLA is deactivated
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* MULA > 0: The PLLA Clock frequency is the PLLA input frequency
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* multiplied by MULA + 1.
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/* Get the PLLA multiplier (MULA)
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*
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* MULA = 0: PLLA is deactivated
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* MULA > 0: The PLLA Clock frequency is the PLLA input frequency
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* multiplied by MULA + 1.
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*/
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mula = (regval & PMC_CKGR_PLLAR_MUL_MASK) >> PMC_CKGR_PLLAR_MUL_SHIFT;
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