SAMA Touchscreen/ADC: More progress
This commit is contained in:
Gregory Nutt
parent
0ff3852b2f
commit
97a4ecb306
@ -50,7 +50,9 @@
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****************************************************************************************/
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/* General definitions ******************************************************************/
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#define SAM_ADC_NCHANNELS 12 /* 12 ADC Channels */
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#define SAM_ADC_NCHANNELS 12 /* 12 ADC Channels */
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#define SAM_ADC_MAXPERCLK 66000000 /* Maximum peripheral clock frequency */
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#define SAM_ADC_CLOCKMAX 20000000 /* Maximum ADC Clock Frequency (Hz) */
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/* ADC register offsets ****************************************************************/
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@ -263,6 +265,10 @@
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#define ADC_CH10 (1 << 10) /* Bit 10: Channel 10 Enable */
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#define ADC_CH11 (1 << 11) /* Bit 11: Channel 11 Enable */
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#define TSD_4WIRE_ALL (0x0000000f)
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#define TSD_5WIRE_ALL (0x0000001f)
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#define ADC_CHALL (0x00000fff)
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/* Last Converted Data Register */
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#define ADC_LCDR_DATA_SHIFT (0) /* Bits 0-11: Last Data Converted */
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@ -448,7 +454,7 @@
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# define ADC_TSMR_TSSCTIM(n) ((uint32_t)(n) << ADC_TSMR_TSSCTIM_SHIFT)
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#define ADC_TSMR_NOTSDMA (1 << 22) /* Bit 22: No TouchScreen DMA */
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#define ADC_TSMR_PENDET (1 << 24) /* Bit 24: Pen Contact Detection Enable */
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#define ADC_TSMR_PENDBC_SHIFT (28) /* Bit 28-31: Pen Detect Debouncing Period */
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#define ADC_TSMR_PENDBC_SHIFT (28) /* Bit 28-31: Pen Detect Debouncing Period */
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#define ADC_TSMR_PENDBC_MASK (15 << ADC_TSMR_PENDBC_SHIFT)
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# define ADC_TSMR_PENDBC(n) ((uint32_t)(n) << ADC_TSMR_PENDBC_SHIFT)
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@ -465,7 +471,7 @@
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#define ADC_YPOSR_YPOS_MASK (0xfff << ADC_YPOSR_YPOS_SHIFT)
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#define ADC_YPOSR_YSCALE_SHIFT (16) /* Bit 16-27: Scale of YPOS */
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#define ADC_YPOSR_YSCALE_MASK (0xfff << ADC_YPOSR_YSCALE_SHIFT)
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0xfff
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/* Touchscreen Pressure Register */
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#define ADC_PRESSR_Z1_SHIFT (0) /* Bit 0-11: Data of Z1 Measurement */
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@ -4,6 +4,16 @@
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* SAMA5D3 Series Data Sheet
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* Atmel NoOS sample code.
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*
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* The Atmel sample code has a BSD compatibile license that requires this
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* copyright notice:
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*
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* Copyright (c) 2012, Atmel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -14,8 +24,8 @@
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* 3. Neither the names NuttX nor Atmel nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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@ -58,6 +68,7 @@
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#include "chip.h"
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#include "chip/sam_adc.h"
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#include "chip/sam_pmc.h"
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#include "sam_dmac.h"
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#include "sam_adc.h"
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@ -125,6 +136,16 @@
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SAMA5_CHAN6_ENABLE || SAMA5_CHAN7_ENABLE || SAMA5_CHAN8_ENABLE || \
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SAMA5_CHAN9_ENABLE || SAMA5_CHAN10_ENABLE || SAMA5_CHAN11_ENABLE)
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#ifdef CONFIG_SAMA5_TOUCHSCREEN
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# ifdef CONFIG_SAMA5_TSD_5WIRE
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# SAMA5_ADC_CHALL (ADC_CHALL & ~TSD_5WIRE_ALL)
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# else
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# SAMA5_ADC_CHALL (ADC_CHALL & ~TSD_4WIRE_ALL)
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# endif
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#else
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# SAMA5_ADC_CHALL ADC_CHALL
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#endif
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/* DMA configuration flags */
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#ifdef CONFIG_SAMA5_ADC_DMA
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@ -138,7 +159,53 @@
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DMACH_FLAG_MEMCHUNKSIZE_1)
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#endif
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#define ADC_CLOCK_MAX 20000000 /* Max ADC Clock Frequency (Hz) */
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/* Pick an unused channel number */
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#if defined(CONFIG_SAMA5_ADC_CHAN0)
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# define SAMA5_ADC_UNUSED 0
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#elif defined(CONFIG_SAMA5_ADC_CHAN1)
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# define SAMA5_ADC_UNUSED 1
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#elif defined(CONFIG_SAMA5_ADC_CHAN2)
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# define SAMA5_ADC_UNUSED 2
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#elif defined(CONFIG_SAMA5_ADC_CHAN3)
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# define SAMA5_ADC_UNUSED 3
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#elif defined(CONFIG_SAMA5_ADC_CHAN4)
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# define SAMA5_ADC_UNUSED 4
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#elif defined(CONFIG_SAMA5_ADC_CHAN5)
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# define SAMA5_ADC_UNUSED 5
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#elif defined(CONFIG_SAMA5_ADC_CHAN6)
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# define SAMA5_ADC_UNUSED 6
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#elif defined(CONFIG_SAMA5_ADC_CHAN7)
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# define SAMA5_ADC_UNUSED 7
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#elif defined(CONFIG_SAMA5_ADC_CHAN8)
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# define SAMA5_ADC_UNUSED 8
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#elif defined(CONFIG_SAMA5_ADC_CHAN9)
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# define SAMA5_ADC_UNUSED 9
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#elif defined(CONFIG_SAMA5_ADC_CHAN10)
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# define SAMA5_ADC_UNUSED 10
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#elif defined(CONFIG_SAMA5_ADC_CHAN11)
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# define SAMA5_ADC_UNUSED 11
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#else
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# undef SAMA5_ADC_UNUSED
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#endif
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/* Clocking */
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#if BOARD_MCK_FREQUENCY <= SAM_ADC_MAXPERCLK
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# define ADC_FREQUENCY BOARD_MCK_FREQUENCY
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# define ADC_PCR_DIV PMC_PCR_DIV1
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#elif (BOARD_MCK_FREQUENCY >> 1) <= SAM_ADC_MAXPERCLK
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# define ADC_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
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# define ADC_PCR_DIV PMC_PCR_DIV2
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#elif (BOARD_MCK_FREQUENCY >> 2) <= SAM_ADC_MAXPERCLK
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# define ADC_FREQUENCY (BOARD_MCK_FREQUENCY >> 2)
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# define ADC_PCR_DIV PMC_PCR_DIV4
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#elif (BOARD_MCK_FREQUENCY >> 3) <= SAM_ADC_MAXPERCLK
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# define ADC_FREQUENCY (BOARD_MCK_FREQUENCY >> 3)
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# define ADC_PCR_DIV PMC_PCR_DIV8
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#else
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# error Cannot realize ADC input frequency
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#endif
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/****************************************************************************
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* Private Types
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@ -202,6 +269,11 @@ static int sam_adc_setup(struct adc_dev_s *dev);
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static void sam_adc_shutdown(struct adc_dev_s *dev);
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static void sam_adc_rxint(struct adc_dev_s *dev, bool enable);
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static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg);
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/* Initialization/Configuration */
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static void sam_adc_sequencer(struct sam_tsd_s *priv);
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static void sam_adc_channels(truct sam_tsd_s *priv);
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#endif
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/****************************************************************************
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@ -547,24 +619,28 @@ static int sam_adc_interrupt(int irq, void *context)
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static void sam_adc_reset(struct adc_dev_s *dev)
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{
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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irqstate_t flags;
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uint32_t regval;
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#ifdef CONFIG_SAMA5_ADC_DMA
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/* Stop any ongoing DMA */
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/* NOTE: We can't really reset the ADC hardware without losing the
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* touchscreen configuration.
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*/
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sam_dmastop(priv->dma);
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#endif
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/* Disable all EOC interrupts */
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/* Reset the ADC controller */
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sam_adc_putreg(priv, SAM_ADC_IDR, ADC_INT_EOCALL);
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flags = irqsave();
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sam_adc_putreg(priv, SAM_ADC_CR, ADC_CR_SWRST);
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/* Disable all channels */
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/* Reset Mode Register */
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sam_adc_putreg(priv, SAM_ADC_CHDR, SAMA5_ADC_CHALL);
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sam_adc_putreg(priv, SAM_ADC_MR, 0);
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irqrestore(flags);
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/* Disable the sequencer */
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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regval &= ~ADC_MR_USEQ;
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sam_adc_putreg(priv, SAM_ADC_MR, regval);
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/* Gain, offset, autocal, trigger mode, etc */
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#warning Missing logic
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}
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/****************************************************************************
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@ -583,6 +659,30 @@ static int sam_adc_setup(struct adc_dev_s *dev)
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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int ret;
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/* Enable (or disable) the sequencer */
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sam_adc_sequencer(priv);
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/* Enable ADC channels */
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sam_adc_channels(priv);
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/* Set gain and offset (only single ended mode used here) */
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#warning Missing logic
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/* Set Auto Calibration Mode*/
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#warning Missing logic
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#ifdef CONFIG_SAMA5_ADC_DMA
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/* Configure for DMA transfer */
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#warning Missing logic
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#else
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/* Enable end-of-conversion interrupts for all enabled channels. */
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#warning Missing logic
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#endif
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/* Attach the ADC interrupt */
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ret = irq_attach(SAM_IRQ_ADC, sam_adc_interrupt);
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@ -595,6 +695,10 @@ static int sam_adc_setup(struct adc_dev_s *dev)
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/* Enable the ADC interrupt */
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up_enable_irq(SAM_IRQ_ADC);
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/* Configure trigger mode and start convention */
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#warning Missing logic
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return OK;
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}
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@ -655,7 +759,7 @@ static void sam_adc_rxint(struct adc_dev_s *dev, bool enable)
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* Name: sam_adc_ioctl
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*
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* Description:
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* All ioctl calls will be routed through this method
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* All ioctl calls will be routed through this method
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*
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****************************************************************************/
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@ -666,6 +770,206 @@ static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
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return -ENOTTY;
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}
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/****************************************************************************
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* Name: sam_adc_sequencer
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*
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* Description:
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* Configure and enable the sequencer
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_ADC_SEQUENCER
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static void sam_adc_setseqr(int chan, uint32_t *seqr1, uint32_t *seqr2, int seq)
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{
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if (seq > 8)
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{
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*seqr2 |= ADC_SEQR2_USCH(seq, chan);
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}
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else
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{
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*seqr1 |= ADC_SEQR1_USCH(seq, chan);
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}
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}
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#endif
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static void sam_adc_sequencer(truct sam_tsd_s *priv)
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{
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#ifdef CONFIG_SAMA5_ADC_SEQUENCER
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uint32_t seqr1;
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uint32_t seqr2;
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int seq;
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/* Set user configured channel sequence */
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seqr1 = 0;
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seqr2 = 0;
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seq = 0;
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#ifdef CONFIG_SAMA5_ADC_CHAN0
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sam_adc_setseqr(0, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN1
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sam_adc_setseqr(1, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN2
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sam_adc_setseqr(2, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN3
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sam_adc_setseqr(3, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN4
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sam_adc_setseqr(4, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN5
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sam_adc_setseqr(5, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN6
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sam_adc_setseqr(6, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN7
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sam_adc_setseqr(7, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN8
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sam_adc_setseqr(8, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN9
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sam_adc_setseqr(9, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN10
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sam_adc_setseqr(10, &seqr1, &seqr2, seq++);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN11
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sam_adc_setseqr(11, &seqr1, &seqr2, seq++);
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#endif
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/* If not all channels are used, then program an unused channel number
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* into the remaining slots. If we don't do this, we will get multiple
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* samples for the enabled channels.
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*/
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#ifdef SAMA5_ADC_UNUSED
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for (; seq < 9; seq++)
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{
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seqr1 |= ADC_SEQR1_USCH(seq, SAMA5_ADC_UNUSED);
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}
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for (; seq < 12; seq++)
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{
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seqr2 |= ADC_SEQR2_USCH(seq, SAMA5_ADC_UNUSED);
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}
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#endif
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/* Save the new values to the SEQR1 and SEQR2 registers */
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sam_adc_putreg(priv, SAM_ADC_SEQR1, seqr1);
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sam_adc_putreg(priv, SAM_ADC_SEQR2, seqr2);
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/* Enable sequencer. Any channel that is not enabled will be skipped by
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* the sequencer (that is why we programmed the unused channels above.
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*/
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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regval |= ADC_MR_USEQ;
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sam_adc_putreg(priv, SAM_ADC_MR, regval);
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#else
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uint32_t regval;
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/* Disable the sequencer */
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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regval &= ~ADC_MR_USEQ;
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sam_adc_putreg(priv, SAM_ADC_MR, regval);
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#endif
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}
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#endif
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/****************************************************************************
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* Name: sam_adc_channels
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*
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* Description:
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* Configure and enable the channels
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*
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****************************************************************************/
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static void sam_adc_channels(truct sam_tsd_s *priv)
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{
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uint32_t regval;
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/* Disable the sequencer */
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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regval &= ~ADC_MR_USEQ;
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sam_adc_putreg(priv, SAM_ADC_MR, regval);
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/* Enable channels. */
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regval = 0;
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#ifdef CONFIG_SAMA5_ADC_CHAN0
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN1
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN2
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN3
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN4
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN5
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN6
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN7
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN8
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN9
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN10
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regval |= ADC_CH0;
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN11
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regval |= ADC_CH0;
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#endif
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sam_adc_putreg(priv, SAM_ADC_CHER, regval);
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -683,9 +987,9 @@ static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
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struct adc_dev_s *sam_adc_initialize(void)
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{
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/* Enable the ADC peripheral clock*/
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/* Disable ADC peripheral clock */
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sam_adc_enableclk();
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sam_adc_disableclk();
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/* Configure ADC pins */
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@ -740,6 +1044,15 @@ struct adc_dev_s *sam_adc_initialize(void)
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||||
DEBUGASSERT(priv->dma);
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||||
#endif
|
||||
|
||||
/* Set the maximum ADC peripheral clock frequency */
|
||||
|
||||
regval = PMC_PCR_PID(SAM_PID_ADC) | PMC_PCR_CMD | ADC_PCR_DIV | PMC_PCR_EN;
|
||||
sam_adc_putreg(priv, SAM_PMC_PCR, regval);
|
||||
|
||||
/* Enable the ADC peripheral clock*/
|
||||
|
||||
sam_adc_enableclk();
|
||||
|
||||
/* Reset the ADC controller */
|
||||
|
||||
sam_adc_putreg(priv, SAM_ADC_CR, ADC_CR_SWRST);
|
||||
@ -748,6 +1061,32 @@ struct adc_dev_s *sam_adc_initialize(void)
|
||||
|
||||
sam_adc_putreg(priv, SAM_ADC_MR, 0);
|
||||
|
||||
/* Set the MCK clock prescaler: ADCClock = MCK / ((PRESCAL+1)*2) */
|
||||
|
||||
regval = sam_adc_getreg(priv, SAM_ADC_MR);
|
||||
regval &= ~ADC_MR_PRESCAL_MASK;
|
||||
regval |= ADC_MR_PRESCAL(BOARD_ADC_PRESCAL);
|
||||
sam_adc_putreg(priv, SAM_ADC_MR, regval);
|
||||
|
||||
/* Formula:
|
||||
* Startup Time = startup value / ADCClock
|
||||
* Transfer Time = (TRANSFER * 2 + 3) / ADCClock
|
||||
* Tracking Time = (TRACKTIM + 1) / ADCClock
|
||||
* Settling Time = settling value / ADCClock
|
||||
* For example, ADC clock = 6MHz (166.7 ns)
|
||||
* Startup time = 512 / 6MHz = 85.3 us
|
||||
* Transfer Time = (1 * 2 + 3) / 6MHz = 833.3 ns
|
||||
* Tracking Time = (0 + 1) / 6MHz = 166.7 ns
|
||||
* Settling Time = 3 / 6MHz = 500 ns
|
||||
*/
|
||||
|
||||
/* Set ADC timing */
|
||||
|
||||
regval = sam_adc_getreg(priv, SAM_ADC_MR);
|
||||
regval &= ~(ADC_MR_STARTUP_MASK | ADC_MR_TRACKTIM_MASK | ADC_MR_SETTLING_MASK);
|
||||
regval |= ADC_MR_STARTUP_SUT512 | ADC_MR_TRACKTIM(0) | ADC_MR_SETTLING_AST17;
|
||||
sam_adc_puttreg(priv, SAM_ADC_MR, regval);
|
||||
|
||||
/* Return a pointer to the device structure */
|
||||
|
||||
return &g_adcdev;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -50,6 +50,10 @@
|
||||
****************************************************************************/
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA_TSD_RXP
|
||||
# define CONFIG_SAMA_TSD_RXP 6
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
@ -155,6 +155,9 @@
|
||||
*/
|
||||
|
||||
#define BOARD_ADC_PRESCAL (7)
|
||||
#define BOARD_TSD_STARTUP (40 /* 40 nanoseconds */
|
||||
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
|
||||
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (unis nanoseconds) */
|
||||
|
||||
/* Resulting frequencies */
|
||||
|
||||
|
||||
@ -113,6 +113,9 @@
|
||||
*/
|
||||
|
||||
#define BOARD_ADC_PRESCAL (7)
|
||||
#define BOARD_TSD_STARTUP (40 /* 40 nanoseconds */
|
||||
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
|
||||
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (unis nanoseconds) */
|
||||
|
||||
/* Resulting frequencies */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user