diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1.h b/arch/arm/src/stm32/hardware/stm32_adc_v1.h
index 9f169f51ad..de4a08044d 100644
--- a/arch/arm/src/stm32/hardware/stm32_adc_v1.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc_v1.h
@@ -49,6 +49,8 @@
  * Pre-processor Definitions
  ****************************************************************************************************/
 
+/* Configuration ************************************************************************************/
+
 /* This is implementation for STM32 ADC IPv1 - F1, F2, F37x, F4, F7.
  * NOTE: L1 use modified IPv1 (look at chip/stm32_adc_v1l1.h).
  */
@@ -80,6 +82,8 @@
 #  undef HAVE_ADC_VBAT
 #endif
 
+/* Base addresses ***********************************************************************************/
+
 /* For the basic ADC IPv1, the ADCx_BASE definitions are defined in chip/stm32xxx_memorymap.h files */
 
 #ifndef HAVE_BASIC_ADC
diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h b/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h
index b0bf9589af..9c804f1353 100644
--- a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h
@@ -45,6 +45,12 @@
 
 #include "chip.h"
 
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Configuration ************************************************************************************/
+
 /* This is implementation for STM32 ADC IPv1 modified for L1 */
 
 #define HAVE_IP_ADC_V1
@@ -66,9 +72,7 @@
 #  define HAVE_ADC_POWERDOWN
 #endif
 
-/****************************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************************/
+/* Base addresses ***********************************************************************************/
 
 #define STM32_ADC1_OFFSET            0x0000
 #define STM32_ADC2_OFFSET            0x0100
diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/stm32/hardware/stm32_adc_v2.h
index efd57a4fdc..61b1eee354 100644
--- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc_v2.h
@@ -45,6 +45,12 @@
 
 #include "chip.h"
 
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Configuration ************************************************************************************/
+
 /* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), H7, L0, L4, L4+ */
 
 #define HAVE_IP_ADC_V2
@@ -78,9 +84,7 @@
 #  define HAVE_ADC_CFGR2
 #endif
 
-/****************************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************************/
+/* Base addresses ***********************************************************************************/
 
 #define STM32_ADC1_OFFSET            0x0000
 #define STM32_ADC2_OFFSET            0x0100