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arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and

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irq.c

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2021-08-05 14:44:48 +02:00 committed by Gustavo Henrique Nihei
parent 633cdf8e27
commit 97dca8fe10
3 changed files with 20 additions and 10 deletions
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10
arch/xtensa/src/esp32/esp32_cpuint.c
View File

@ -154,6 +154,16 @@ uint8_t g_cpu0_intmap[ESP32_NCPUINTS];
uint8_t g_cpu1_intmap[ESP32_NCPUINTS];
#endif
/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
* content.
*/
#ifdef CONFIG_SMP
uint32_t g_intenable[CONFIG_SMP_NCPUS];
#else
uint32_t g_intenable[1];
#endif
/****************************************************************************
* Private Data
****************************************************************************/

10
arch/xtensa/src/esp32/esp32_cpuint.h
View File

@ -46,6 +46,16 @@ extern uint8_t g_cpu0_intmap[ESP32_NCPUINTS];
extern uint8_t g_cpu1_intmap[ESP32_NCPUINTS];
#endif
/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
* content.
*/
#ifdef CONFIG_SMP
extern uint32_t g_intenable[CONFIG_SMP_NCPUS];
#else
extern uint32_t g_intenable[1];
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/

10
arch/xtensa/src/esp32/esp32_irq.c
View File

@ -59,16 +59,6 @@
* Public Data
****************************************************************************/
/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
* content.
*/
#ifdef CONFIG_SMP
static uint32_t g_intenable[CONFIG_SMP_NCPUS];
#else
static uint32_t g_intenable[1];
#endif
/* g_current_regs[] holds a reference to the current interrupt level
* register storage structure. It is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro