SAMA5D4: Fix peripheral clocking macros: AIC and L2CC are continuously clocked
This commit is contained in:
Gregory Nutt
parent
c14d80ee25
commit
9869c9b50d
@ -128,9 +128,19 @@ static void sam_dumpaic(const char *msg, int irq)
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lldbg(" IPR: %08x %08x %08x %08x\n",
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getreg32(SAM_AIC_IPR0), getreg32(SAM_AIC_IPR1),
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getreg32(SAM_AIC_IPR2), getreg32(SAM_AIC_IPR3));
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/* SAMA5D4 does not have the FFSR register */
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#ifdef SAM_AIC_FFSR
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lldbg(" IMR: %08x CISR: %08x SPU: %08x FFSR: %08x\n",
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getreg32(SAM_AIC_IMR), getreg32(SAM_AIC_CISR),
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getreg32(SAM_AIC_SPU), getreg32(SAM_AIC_FFSR));
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#else
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lldbg(" IMR: %08x CISR: %08x SPU: %08x\n",
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getreg32(SAM_AIC_IMR), getreg32(SAM_AIC_CISR),
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getreg32(SAM_AIC_SPU));
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#endif
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lldbg(" DCR: %08x WPMR: %08x WPSR: %08x\n",
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getreg32(SAM_AIC_DCR), getreg32(SAM_AIC_WPMR),
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getreg32(SAM_AIC_WPSR));
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@ -191,7 +201,7 @@ static inline size_t sam_vectorsize(void)
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static uint32_t *sam_spurious(int irq, uint32_t *regs)
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{
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/* This is probably irrevelant since true vectored interrupts are not used
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/* This is probably irrelevant since true vectored interrupts are not used
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* in this implementation. The value of AIC_IVR is ignored.
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*/
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@ -211,7 +221,7 @@ static uint32_t *sam_spurious(int irq, uint32_t *regs)
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static uint32_t *sam_fiqhandler(int irq, uint32_t *regs)
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{
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/* This is probably irrevelant since FIQs are not used in this
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/* This is probably irrelevant since FIQs are not used in this
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* implementation.
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*/
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@ -439,7 +449,7 @@ void up_irqinitialize(void)
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* the irq number of the interrupt and then to call arm_doirq to dispatch
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* the interrupt.
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*
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* Input paramters:
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* Input parameters:
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* regs - A pointer to the register save area on the stack.
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*
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****************************************************************************/
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@ -73,12 +73,12 @@
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/* 32-bit Encoding:
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*
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* ..MM MCCC CCDD IIIV PPPB BBBB
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* .... .... ..MM MCCC CCDD IIIV PPPB BBBB
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*/
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/* Input/Output mode:
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*
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* ..MM M... .... .... .... ....
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* .... .... ..MM M... .... .... .... ....
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*/
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#define PIO_MODE_SHIFT (19) /* Bits 19-21: PIO mode */
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@ -93,7 +93,7 @@
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/* These bits set the configuration of the pin:
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* NOTE: No definitions for parallel capture mode
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*
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* .... .CCC CC.. .... .... ....
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* .... .... .... .CCC CC.. .... .... ....
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*/
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#define PIO_CFG_SHIFT (14) /* Bits 14-18: PIO configuration bits */
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@ -107,7 +107,7 @@
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/* Drive Strength:
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*
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* .... .... ..DD .... .... ....
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* .... .... .... .... ..DD .... .... ....
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*/
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#define PIO_DRIVE_SHIFT (12) /* Bits 12-13: Drive strength */
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@ -118,7 +118,7 @@
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/* Additional interrupt modes:
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*
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* .... .... .... III. .... ....
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* .... .... .... .... .... III. .... ....
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*/
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#define PIO_INT_SHIFT (9) /* Bits 9-11: PIO interrupt bits */
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@ -137,7 +137,7 @@
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/* If the pin is an PIO output, then this identifies the initial output value:
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*
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* .... .... .... ...V .... ....
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* .... .... .... .... .... ...V .... ....
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*/
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#define PIO_OUTPUT_SET (1 << 8) /* Bit 8: Inital value of output */
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@ -145,7 +145,7 @@
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/* This identifies the PIO port:
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*
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* .... .... .... .... PPP. ....
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* .... .... .... .... .... .... PPP. ....
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*/
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#define PIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
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@ -158,7 +158,7 @@
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/* This identifies the bit in the port:
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*
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* .... .... .... .... ...B BBBB
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* .... .... .... .... .... .... ...B BBBB
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*/
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#define PIO_PIN_SHIFT (0) /* Bits 0-4: PIO number: 0-31 */
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@ -52,13 +52,10 @@
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#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
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#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
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#define sam_enableperiph2(s) putreg32((1 << ((s) - 64)), SAM_PMC_PCER2)
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#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
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#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
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#define sam_disableperiph2(s) putreg32((1 << ((s) - 63)), SAM_PMC_PCDR2)
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#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
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#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
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#define sam_isenabled2(s) (getreg32(SAM_PMC_PCER2) & (1 << ((s) - 64)) != 0)
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/* Enable peripheral clocking */
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@ -122,10 +119,18 @@
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#define sam_twi3_enableclk() sam_enableperiph1(SAM_PID_TWI3)
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#define sam_catb_enableclk() sam_enableperiph1(SAM_PID_CATB)
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#define sam_sfr_enableclk() sam_enableperiph2(SAM_PID_CATB)
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#define sam_aic_enableclk() sam_enableperiph2(SAM_PID_CATB)
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#define sam_saic_enableclk() sam_enableperiph2(SAM_PID_CATB)
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#define sam_l2cc_enableclk() sam_enableperiph2(SAM_PID_CATB)
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/* The Advanced Interrupt Controller and L2CC cache controllers are
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* continuously clocked. The Power Management Controller has no effect on
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* their behavior.
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*
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* (I presume that this is true of the SFR as well since it has no PMC
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* bits to control its clocking).
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*/
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#define sam_sfr_enableclk()
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#define sam_aic_enableclk()
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#define sam_saic_enableclk()
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#define sam_l2cc_enableclk()
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/* Disable peripheral clocking */
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@ -189,10 +194,18 @@
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#define sam_twi3_disableclk() sam_disableperiph1(SAM_PID_TWI3)
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#define sam_catb_disableclk() sam_disableperiph1(SAM_PID_CATB)
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#define sam_sfr_disableclk() sam_disableperiph2(SAM_PID_CATB)
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#define sam_aic_disableclk() sam_disableperiph2(SAM_PID_CATB)
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#define sam_saic_disableclk() sam_disableperiph2(SAM_PID_CATB)
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#define sam_l2cc_disableclk() sam_disableperiph2(SAM_PID_CATB)
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/* The Advanced Interrupt Controller and L2CC cache controllers are
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* continuously clocked. The Power Management Controller has no effect on
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* their behavior.
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*
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* (I presume that this is true of the SFR as well since it has no PMC
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* bits to control its clocking).
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*/
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#define sam_sfr_disableclk()
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#define sam_aic_disableclk()
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#define sam_saic_disableclk()
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#define sam_l2cc_disableclk()
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/* Test if peripheral clocking is enabled */
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@ -256,10 +269,18 @@
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#define sam_twi3_isenabled() sam_isenabled1(SAM_PID_TWI3)
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#define sam_catb_isenabled() sam_isenabled1(SAM_PID_CATB)
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#define sam_sfr_isenabled() sam_isenabled2(SAM_PID_CATB)
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#define sam_aic_isenabled() sam_isenabled2(SAM_PID_CATB)
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#define sam_saic_isenabled() sam_isenabled2(SAM_PID_CATB)
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#define sam_l2cc_isenabled() sam_isenabled2(SAM_PID_CATB)
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/* The Advanced Interrupt Controller and L2CC cache controllers are
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* continuously clocked. The Power Management Controller has no effect on
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* their behavior.
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*
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* (I presume that this is true of the SFR as well since it has no PMC
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* bits to control its clocking).
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*/
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#define sam_sfr_isenabled() (true)
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#define sam_aic_isenabled() (true)
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#define sam_saic_isenabled() (true)
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#define sam_l2cc_isenabled() (true)
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/************************************************************************************
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* Public Types
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