Finishes basic header file updates for STM3230
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4114 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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229
arch/arm/src/stm32/chip/stm32_uart.h
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229
arch/arm/src/stm32/chip/stm32_uart.h
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@ -0,0 +1,229 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_uart.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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||||
* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32_UART_H
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#define __ARCH_ARM_STC_STM32_CHIP_STM32_UART_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
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#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
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#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
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#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
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#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
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#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
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#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
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/* Register Addresses ***************************************************************/
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#if STM32_NUSART > 0
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# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 1
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# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 2
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# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 3
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# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
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# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
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# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
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#endif
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#if STM32_NUSART > 4
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# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
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# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
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# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
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#endif
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#if STM32_NUSART > 5
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# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* Status register */
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#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
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#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
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#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
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#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
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#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
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#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
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#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
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#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
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#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
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#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
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#define USART_SR_ALLBITS (0x03ff)
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#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
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/* Data register */
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#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
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#define USART_DR_MASK (0xff << USART_DR_SHIFT)
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/* Baud Rate Register */
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#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
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#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
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#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
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#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
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/* Control register 1 */
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#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
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#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
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#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
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#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
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#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
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#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
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#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
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#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
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#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
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#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
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#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
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#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
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#define USART_CR1_M (1 << 12) /* Bit 12: word length */
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#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
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#ifdef CONFIG_STM32_STM32F40XX
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# define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
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#endif
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#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
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/* Control register 2 */
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#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
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#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
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#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
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#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
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#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
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#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
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#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
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#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
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#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
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#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
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# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
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# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
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# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
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# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
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#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
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/* Control register 3 */
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#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
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#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
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#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
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#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
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#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
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#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
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#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
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#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
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#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
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#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
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#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
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#ifdef CONFIG_STM32_STM32F40XX
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# define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
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#endif
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/* Guard time and prescaler register */
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#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
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#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
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#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
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#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32_UART_H */
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@ -2,7 +2,7 @@
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* arch/arm/src/stm32/chip/stm32_usbdev.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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136
arch/arm/src/stm32/chip/stm32_wdg.h
Normal file
136
arch/arm/src/stm32/chip/stm32_wdg.h
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@ -0,0 +1,136 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_wdg.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_WDG_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_WDG_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
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#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
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#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
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#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
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#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
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#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
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#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
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/* Register Addresses ***************************************************************/
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#define STM32_IWDG_KR (STM32_IWDG_OFFSET+STM32_IWDG_KR_OFFSET)
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#define STM32_IWDG_PR (STM32_IWDG_OFFSET+STM32_IWDG_PR_OFFSET)
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#define STM32_IWDG_RLR (STM32_IWDG_OFFSET+STM32_IWDG_RLR_OFFSET)
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#define STM32_IWDG_SR (STM32_IWDG_OFFSET+STM32_IWDG_SR_OFFSET)
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#define STM32_WWDG_CR (STM32_WWDG_OFFSET+STM32_WWDG_CR_OFFSET)
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#define STM32_WWDG_CFR (STM32_WWDG_OFFSET+STM32_WWDG_CFR_OFFSET)
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#define STM32_WWDG_SR (STM32_WWDG_OFFSET+STM32_WWDG_SR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* Key register (32-bit) */
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#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */
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#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
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/* Prescaler register (32-bit) */
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#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
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#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
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# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
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# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
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# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
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# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
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# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
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# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
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# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
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/* Reload register (32-bit) */
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#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */
|
||||
#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
|
||||
|
||||
/* Status register (32-bit) */
|
||||
|
||||
#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
|
||||
#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
|
||||
|
||||
/* Control Register (32-bit) */
|
||||
|
||||
#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
|
||||
#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
|
||||
#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
|
||||
|
||||
/* Configuration register (32-bit) */
|
||||
|
||||
#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
|
||||
#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
|
||||
#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
|
||||
#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
|
||||
# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
|
||||
# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
|
||||
# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
|
||||
# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
|
||||
#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
|
||||
|
||||
/* Status register (32-bit) */
|
||||
|
||||
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_WDG_H */
|
||||
@ -2,7 +2,7 @@
|
||||
* arch/arm/src/stm32/stm32_uart.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -43,159 +43,12 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_uart.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
|
||||
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
|
||||
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
|
||||
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
|
||||
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
|
||||
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
|
||||
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
|
||||
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
|
||||
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
|
||||
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
|
||||
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
|
||||
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
|
||||
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
|
||||
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
|
||||
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
|
||||
|
||||
#define USART_SR_ALLBITS (0x03ff)
|
||||
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
|
||||
|
||||
/* Data register */
|
||||
|
||||
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
|
||||
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
|
||||
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
|
||||
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
|
||||
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
|
||||
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
|
||||
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
|
||||
|
||||
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
|
||||
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
|
||||
#define USART_CR2_LBDL (1 << 6) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 7) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 15-8: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 7:0 [7:0]: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_wdg.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -43,84 +43,12 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_wdg.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
|
||||
#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
|
||||
#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
|
||||
#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
|
||||
|
||||
#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
|
||||
#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
|
||||
#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_IWDG_KR (STM32_IWDG_OFFSET+STM32_IWDG_KR_OFFSET)
|
||||
#define STM32_IWDG_PR (STM32_IWDG_OFFSET+STM32_IWDG_PR_OFFSET)
|
||||
#define STM32_IWDG_RLR (STM32_IWDG_OFFSET+STM32_IWDG_RLR_OFFSET)
|
||||
#define STM32_IWDG_SR (STM32_IWDG_OFFSET+STM32_IWDG_SR_OFFSET)
|
||||
|
||||
#define STM32_WWDG_CR (STM32_WWDG_OFFSET+STM32_WWDG_CR_OFFSET)
|
||||
#define STM32_WWDG_CFR (STM32_WWDG_OFFSET+STM32_WWDG_CFR_OFFSET)
|
||||
#define STM32_WWDG_SR (STM32_WWDG_OFFSET+STM32_WWDG_SR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Key register (32-bit) */
|
||||
|
||||
#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */
|
||||
#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
|
||||
|
||||
/* Prescaler register (32-bit) */
|
||||
|
||||
#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
|
||||
#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
|
||||
# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
|
||||
# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
|
||||
# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
|
||||
# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
|
||||
# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
|
||||
# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
|
||||
# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
|
||||
|
||||
/* Reload register (32-bit) */
|
||||
|
||||
#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */
|
||||
#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
|
||||
|
||||
/* Status register (32-bit) */
|
||||
|
||||
#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
|
||||
#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
|
||||
|
||||
/* Control Register (32-bit) */
|
||||
|
||||
#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
|
||||
#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
|
||||
#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
|
||||
|
||||
/* Configuration register (32-bit) */
|
||||
|
||||
#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
|
||||
#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
|
||||
#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
|
||||
#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
|
||||
# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
|
||||
# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
|
||||
# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
|
||||
# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
|
||||
#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
|
||||
|
||||
/* Status register (32-bit) */
|
||||
|
||||
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user