STM32 F7: Refresh configuration

This commit is contained in:
Gregory Nutt 2015-07-19 09:24:52 -06:00
parent 9a1df49096
commit 98f62d23d5

View File

@ -146,6 +146,8 @@ CONFIG_ARCH_CHIP_STM32F746=y
# CONFIG_ARCH_CHIP_STM32F756 is not set
CONFIG_STM32F7_STM32F74XX=y
# CONFIG_STM32F7_STM32F75XX is not set
# CONFIG_STM32F7_FLASH_512KB is not set
CONFIG_STM32F7_FLASH_1024KB=y
#
# STM32 Peripheral Support
@ -164,6 +166,7 @@ CONFIG_STM32F7_USART=y
# CONFIG_STM32F7_BKPSRAM is not set
# CONFIG_STM32F7_CAN1 is not set
# CONFIG_STM32F7_CAN2 is not set
# CONFIG_STM32F7_CEC is not set
# CONFIG_STM32F7_CRC is not set
# CONFIG_STM32F7_CRYP is not set
# CONFIG_STM32F7_DMA1 is not set
@ -176,13 +179,14 @@ CONFIG_STM32F7_USART=y
# CONFIG_STM32F7_I2C1 is not set
# CONFIG_STM32F7_I2C2 is not set
# CONFIG_STM32F7_I2C3 is not set
# CONFIG_STM32F7_LPTIM1 is not set
# CONFIG_STM32F7_LTDC is not set
# CONFIG_STM32F7_DMA2D is not set
# CONFIG_STM32F7_OTGFS is not set
# CONFIG_STM32F7_OTGHS is not set
CONFIG_STM32F7_PWR=y
# CONFIG_STM32F7_RNG is not set
# CONFIG_STM32F7_QUADSPI is not set
# CONFIG_STM32F7_SAI1 is not set
# CONFIG_STM32F7_RNG is not set
# CONFIG_STM32F7_SAI2 is not set
# CONFIG_STM32F7_SDMMC1 is not set
# CONFIG_STM32F7_SPDIFRX is not set
@ -217,6 +221,7 @@ CONFIG_STM32F7_USART6=y
# CONFIG_STM32F7_UART8 is not set
# CONFIG_STM32F7_IWDG is not set
# CONFIG_STM32F7_WWDG is not set
# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
#
# Architecture Options