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SAMA5 LCDC: Correct how framebuffer memory was being mapped; Remove options to get framebuffer memory in various. Because of the mapping and aligment requirements, those options really cannot be supported

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This commit is contained in:
Gregory Nutt 2013-10-13 13:08:05 -06:00
parent a3bb8d3d94
commit 98ffd096a0
8 changed files with 331 additions and 634 deletions
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4
arch/arm/src/armv7-a/arm_mmu.c
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@ -146,7 +146,7 @@ void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
#endif
/****************************************************************************
* Name: mmu_l2_map_region
* Name: mmu_l1_map_region
*
* Description:
* Set multiple level 1 translation table entries in order to map a
@ -158,7 +158,7 @@ void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l2_map_region(const struct section_mapping_s *mapping)
void mmu_l1_map_region(const struct section_mapping_s *mapping)
{
uint32_t paddr = mapping->physbase;
uint32_t vaddr = mapping->virtbase;

4
arch/arm/src/armv7-a/mmu.h
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@ -1322,7 +1322,7 @@ void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags);
#endif
/************************************************************************************
* Name: mmu_l2_map_region
* Name: mmu_l1_map_region
*
* Description:
* Set multiple level 1 translation table entries in order to map a region of
@ -1334,7 +1334,7 @@ void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags);
************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l2_map_region(const struct section_mapping_s *mapping);
void mmu_l1_map_region(const struct section_mapping_s *mapping);
#endif
/****************************************************************************

53
arch/arm/src/sama5/Kconfig
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@ -326,48 +326,25 @@ config SAMA5_LCDC_BACKCOLOR
hex "Background color"
default 0x0
choice
prompt "Frame buffer allocation strategy"
default SAMA5_LCDC_FBALLOCATED
config SAMA5_LCDC_FBALLOCATED
bool "Allocate from heap"
config SAMA5_LCDC_FB_VBASE
hex "Framebuffer memory start address (virtual)"
---help---
Allocate frame buffers and layer DMA descriptors from the heap.
If you are using the the LCDC, then you must provide the virtual
address of the start of the framebuffer. This address must be
aligned to a 1MB bounder (i.e., the last five "digits" of the
hexadecimal address must be zero).
WARNING: This data cannot reside in internal SRAM; LCDC DMA only
works with DDR2 and CS0-3.
config SAMA5_LCDC_FBFIXED
bool "Fixed allocation outside the heap"
config SAMA5_LCDC_FB_PBASE
hex "Framebuffer memory start address (virtual)"
---help---
Allocate frame buffers and DMA descriptors at a fixe address outside
of either the heap or .bss lying at this address.
If you are using the the LCDC, then you must provide the physical
address of the start of the framebuffer. This address must be
aligned to a 1MB bounder (i.e., the last five "digits" of the
hexadecimal address must be zero).
WARNING: This data cannot reside in internal SRAM; LCDC DMA only
works with DDR2 and CS0-3.
config SAMA5_LCDC_FBPREALLOCATED
bool "Pre-allocated in .bss"
---help---
Allocate frame buffers and layer DMA descriptors as normal global
variables that will be positioned in .bss.
WARNING: This data cannot reside in internal SRAM; LCDC DMA only
works with DDR2 and CS0-3.
endchoice # Frame buffer allocatin strategy
if SAMA5_LCDC_FBFIXED
config SAMA5_LCDC_FBFIXED_BASE
hex "Framebuffer memory start address"
config SAMA5_LCDC_FBFIXED_SIZE
int "Framebuffer memory size"
default 0
endif # SAMA5_LCDC_FBFIXED
config SAMA5_LCDC_FB_SIZE
int "Framebuffer memory size (bytes)"
default 0
comment "Base layer configuration"

6
arch/arm/src/sama5/chip/sam_lcdc.h
View File

@ -1892,8 +1892,10 @@
struct sam_dscr_s
{
uint32_t addr; /* Frame buffer base address register */
uint32_t ctrl; /* Transfer Control register */
uint32_t next; /* Next descriptor address register */
uint32_t ctrl; /* Transfer Control register */
uint32_t next; /* Next descriptor address register */
uint32_t pad; /* Padding to assure 64-bit aligned when used as an array */
};
#define SIZEOF_SAM_DSCR_S 16
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_LCDC_H */

27
arch/arm/src/sama5/chip/sama5d3x_memorymap.h
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@ -263,13 +263,30 @@
#define SAM_AXIMX_MMUFLAGS MMU_IOFLAGS
#define SAM_DAP_MMUFLAGS MMU_IOFLAGS
#define SAM_EBICS0_MMUFLAGS MMU_MEMFLAGS
#define SAM_DDRCS_MMUFLAGS MMU_MEMFLAGS
#define SAM_EBICS1_MMUFLAGS MMU_MEMFLAGS
#define SAM_EBICS2_MMUFLAGS MMU_MEMFLAGS
#define SAM_EBICS3_MMUFLAGS MMU_MEMFLAGS
#define SAM_NFCCR_MMUFLAGS MMU_IOFLAGS
#if defined(CONFIG_SAMA5_EBICS0_SRAM) || defined(CONFIG_SAMA5_EBICS0_PSRAM)
# define SAM_EBICS0_MMUFLAGS MMU_MEMFLAGS
#else
# define SAM_EBICS0_MMUFLAGS MMU_ROMFLAGS
#endif
#if defined(CONFIG_SAMA5_EBICS1_SRAM) || defined(CONFIG_SAMA5_EBICS1_PSRAM)
# define SAM_EBICS1_MMUFLAGS MMU_MEMFLAGS
#else
# define SAM_EBICS1_MMUFLAGS MMU_ROMFLAGS
#endif
#if defined(CONFIG_SAMA5_EBICS2_SRAM) || defined(CONFIG_SAMA5_EBICS2_PSRAM)
# define SAM_EBICS2_MMUFLAGS MMU_MEMFLAGS
#else
# define SAM_EBICS2_MMUFLAGS MMU_ROMFLAGS
#endif
#if defined(CONFIG_SAMA5_EBICS3_SRAM) || defined(CONFIG_SAMA5_EBICS3_PSRAM)
# define SAM_EBICS3_MMUFLAGS MMU_MEMFLAGS
#else
# define SAM_EBICS3_MMUFLAGS MMU_ROMFLAGS
#endif
#define SAM_NFCCR_MMUFLAGS MMU_IOFLAGS
#define SAM_PERIPHA_MMUFLAGS MMU_IOFLAGS
#define SAM_PERIPHB_MMUFLAGS MMU_IOFLAGS
#define SAM_SYSC_MMUFLAGS MMU_IOFLAGS

148
arch/arm/src/sama5/sam_boot.c
View File

@ -59,6 +59,7 @@
#include "sam_clockconfig.h"
#include "sam_lowputc.h"
#include "sam_serial.h"
#include "sam_lcd.h"
/****************************************************************************
* Pre-processor Definitions
@ -85,6 +86,18 @@
# error High vector remap cannot be performed if we are using a ROM page table
#endif
/* if SDRAM is used, then it will be configured twice: It will first be
* configured to a temporary state to support low-level ininitialization.
* After the SDRAM has been fully initialized, SRAM be used to
* set the SDRM in its final, fully cache-able state.
*/
#undef NEED_SDRAM_REMAPPING
#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM) && \
!defined(CONFIG_ARCH_ROMPGTABLE)
# define NEED_SDRAM_REMAPPING 1
#endif
/****************************************************************************
* Private Types
****************************************************************************/
@ -135,38 +148,50 @@ static const struct section_mapping_s section_mapping[] =
#if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM)
{ CONFIG_FLASH_VSTART, 0x00000000,
MMU_ROMFLAGS, 1 },
MMU_ROMFLAGS, 1
},
#else
{ SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION,
SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS },
SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS
},
#endif
{ SAM_ROM_PSECTION, SAM_ROM_VSECTION,
SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS },
SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS
},
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS },
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
},
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS },
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
},
#endif
{ SAM_SMD_PSECTION, SAM_SMD_VSECTION,
SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS },
SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS
},
{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS },
SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS
},
{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS },
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS
},
{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS },
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS
},
{ SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS },
SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS
},
{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS },
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
},
/* SAMA5 CS0 External Memories */
#ifdef CONFIG_SAMA5_EBICS0
{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS },
SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS
},
#endif
/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
@ -184,10 +209,12 @@ static const struct section_mapping_s section_mapping[] =
#ifdef CONFIG_SAMA5_DDRCS
#ifdef CONFIG_SAMA5_BOOT_SDRAM
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS },
MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS
},
#else
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS },
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
},
#endif
#endif
@ -195,31 +222,54 @@ static const struct section_mapping_s section_mapping[] =
#ifdef CONFIG_SAMA5_EBICS1
{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS },
SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_EBICS2
{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS },
SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_EBICS3
{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS },
SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_NFCCR
{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS },
SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS
},
#endif
/* SAMA5 Internal Peripherals */
{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS },
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
},
{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS },
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
},
{ SAM_SYSC_PSECTION, SAM_SYSC_VSECTION,
SAM_SYSC_MMUFLAGS, SAM_SYSC_NSECTIONS },
SAM_SYSC_MMUFLAGS, SAM_SYSC_NSECTIONS
},
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cacheable and non-buffereable.
*
* If SDRAM will be reconfigured, then we will defer setup of the framebuffer
* until after the SDRAM remapping (since the framebuffer problem resides) in
* SDRAM.
*/
#if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING)
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
},
#endif
};
#define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s))
#define NMAPPINGS \
(sizeof(section_mapping) / sizeof(struct section_mapping_s))
#endif
/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
@ -228,12 +278,30 @@ static const struct section_mapping_s section_mapping[] =
* set the SDRM in its final, fully cache-able state.
*/
#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM)
static const struct section_mapping_s operational_mapping =
#ifdef NEED_SDRAM_REMAPPING
static const struct section_mapping_s operational_mapping[] =
{
SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
/* This entry reprograms the SDRAM entry, making it cacheable and
* bufferable.
*/
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
},
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cacheable and non-buffereable.
*/
#ifdef CONFIG_SAMA5_LCDC
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
},
#endif
};
#define NREMAPPINGS \
(sizeof(operational_mapping) / sizeof(struct section_mapping_s))
#endif
/****************************************************************************
@ -244,7 +312,7 @@ static const struct section_mapping_s operational_mapping =
* Name: sam_setupmappings
*
* Description
* Map all of the memory regions defined in section_mapping[]
* Map all of the initial memory regions defined in section_mapping[]
*
****************************************************************************/
@ -255,7 +323,27 @@ static inline void sam_setupmappings(void)
for (i = 0; i < NMAPPINGS; i++)
{
mmu_l2_map_region(&section_mapping[i]);
mmu_l1_map_region(&section_mapping[i]);
}
}
#endif
/****************************************************************************
* Name: sam_remap
*
* Description
* Map all of the final memory regions defined in operation_mapping[]
*
****************************************************************************/
#ifdef NEED_SDRAM_REMAPPING
static inline void sam_remap(void)
{
int i;
for (i = 0; i < NREMAPPINGS; i++)
{
mmu_l1_map_region(&operational_mapping[i]);
}
}
#endif
@ -561,7 +649,7 @@ void up_boot(void)
* we can reconfigure the SDRAM in its final, fully cache-able state.
*/
#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM)
mmu_l2_map_region(&operational_mapping);
#ifdef NEED_SDRAM_REMAPPING
sam_remap();
#endif
}

706
arch/arm/src/sama5/sam_lcd.c
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File diff suppressed because it is too large Load Diff

17
arch/arm/src/sama5/sam_lcd.h
View File

@ -48,9 +48,25 @@
#include "chip/sam_lcd.h"
#ifdef CONFIG_SAMA5_LCDC
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* These definitions provide the LCDC framebuffer memory description needed to
* remap that region to be non-cacheable and non-bufferable
*/
#if (CONFIG_SAMA5_LCDC_FB_VBASE & 0x000fffff) != 0
# error CONFIG_SAMA5_LCDC_FB_VBASE not aligned to 1MB boundary
#endif
#if (CONFIG_SAMA5_LCDC_FB_PBASE & 0x000fffff) != 0
# error CONFIG_SAMA5_LCDC_FB_PBASE not aligned to 1MB boundary
#endif
#define SAMA5_LCDC_FBNSECTIONS \
((CONFIG_SAMA5_LCDC_FB_SIZE + 0x000fffff) >> 20)
/************************************************************************************
* Public Types
@ -93,4 +109,5 @@ void sam_lcdclear(nxgl_mxpixel_t color);
void sam_backlight(bool blon);
#endif
#endif /* CONFIG_SAMA5_LCDC */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_LCDC_H */