Trivial changes to comments.
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@ -53,16 +53,21 @@
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/* Clocking *************************************************************************/
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/* Default clock initialization
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* fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz
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* => fPERIPH = 144MHz
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* => fCCU = 144MHz
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* => fETH = 72MHz
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* => fUSB = 48MHz
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* => fEBU = 72MHz
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*
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* fXTAL = 12Mhz
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* -> fPLL = (fXTAL / (2 * 1) * 48) = 288MHz
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* -> fSYS = (fPLL / 1) = 288MHz
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* -> fCPU = (fSYS / 2) = 144MHz
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* -> fPERIPH = (fCPU / 1) = 144MHz
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* -> fCCU = (fSYS / 2) = 144MHz
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* -> fETH = 72MHz (REVISIT)
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* -> fUSB = 48MHz (REVISIT)
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* -> fEBU = 72MHz (REVISIT)
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*
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* fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected
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*
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* fOFI = 24MHz => fWDT = 24MHz
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* fOFI = 24MHz
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* -> fWDT = 24MHz (REVISIT)
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*/
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#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */
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