diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig index c71809496c..23d2428e3c 100644 --- a/arch/risc-v/src/esp32c3/Kconfig +++ b/arch/risc-v/src/esp32c3/Kconfig @@ -75,6 +75,16 @@ config ESP32C3_ESP32C3XXX menu "ESP32-C3 Peripheral Support" +config ESP32C3_UART0 + bool "UART0" + default y + select UART0_SERIALDRIVER + +config ESP32C3_UART1 + bool "UART1" + default n + select UART1_SERIALDRIVER + endmenu endif # ARCH_CHIP_ESP32C3 diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs index 4079b26d83..defe8393b7 100644 --- a/arch/risc-v/src/esp32c3/Make.defs +++ b/arch/risc-v/src/esp32c3/Make.defs @@ -51,3 +51,4 @@ endif CHIP_CSRCS = esp32c3_allocateheap.c esp32c3_start.c esp32c3_idle.c CHIP_CSRCS += esp32c3_irq.c esp32c3_timerisr.c +CHIP_CSRCS += esp32c3_serial.c esp32c3_lowputc.c diff --git a/arch/risc-v/src/esp32c3/esp32c3.h b/arch/risc-v/src/esp32c3/esp32c3.h index 299aabae82..a5f83c7236 100644 --- a/arch/risc-v/src/esp32c3/esp32c3.h +++ b/arch/risc-v/src/esp32c3/esp32c3.h @@ -33,7 +33,6 @@ #include #include "riscv_internal.h" #include "riscv_arch.h" -#include "esp32c3_rom.h" #include "chip.h" /**************************************************************************** diff --git a/arch/risc-v/src/esp32c3/esp32c3_rom.h b/arch/risc-v/src/esp32c3/esp32c3_config.h similarity index 51% rename from arch/risc-v/src/esp32c3/esp32c3_rom.h rename to arch/risc-v/src/esp32c3/esp32c3_config.h index e898b9408e..a44c510af0 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rom.h +++ b/arch/risc-v/src/esp32c3/esp32c3_config.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rom.h + * arch/risc-v/src/esp32c3/esp32c3_config.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,19 +18,46 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ROM_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ROM_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CONFIG_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CONFIG_H /**************************************************************************** * Included Files ****************************************************************************/ -#include +#include +#include +#include /**************************************************************************** - * Name: ets_printf + * Pre-processor Definitions ****************************************************************************/ -int ets_printf(const char *fmt, ...); +/* UARTs ********************************************************************/ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ROM_H */ +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_ESP32C3_UART0) || defined(CONFIG_ESP32C3_UART1) +# define HAVE_UART_DEVICE 1 /* Flag to indicate a UART has been selected */ +#endif + +/* Serial Console ***********************************************************/ + +/* Is there a serial console? There should be no more than one defined. It + * could be on any UARTn. n E {0,1} + */ + +#undef HAVE_SERIAL_CONSOLE +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32C3_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32C3_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32C3_ESP32C3_CONFIG_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_lowputc.c b/arch/risc-v/src/esp32c3/esp32c3_lowputc.c new file mode 100644 index 0000000000..63d91ac845 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_lowputc.c @@ -0,0 +1,394 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "hardware/esp32c3_uart.h" +#include "riscv_arch.h" +#include "chip.h" +#include "esp32c3_lowputc.h" +#include "esp32c3_config.h" +#include "hardware/esp32c3_soc.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) + +static const struct esp32c3_uart_s g_console_config = +{ + .base = REG_UART_BASE(0), + .id = 0, + .irq = -1, /* TODO */ + .baud = CONFIG_UART0_BAUD, + .bits = CONFIG_UART0_BITS, + .parity = CONFIG_UART0_PARITY, + .stop_b2 = CONFIG_UART0_2STOP, + .int_pri = 1 +}; + +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) + +static const struct esp32c3_uart_s g_uart1_config = +{ + .base = REG_UART_BASE(1), + .id = 1, + .irq = -1, /* TODO */ + .baud = CONFIG_UART1_BAUD, + .bits = CONFIG_UART1_BITS, + .parity = CONFIG_UART1_PARITY, + .stop_b2 = CONFIG_UART1_2STOP, + .int_pri = 1 +}; +#endif /* CONFIG_UART0_SERIAL_CONSOLE */ +#endif /* HAVE_SERIAL_CONSOLE */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_lowputc_reset_core + * Reset both TX and RX core + ****************************************************************************/ + +void esp32c3_lowputc_reset_core(const struct esp32c3_uart_s *conf) +{ + uint32_t set_bit = 1 << UART_RST_CORE_S; + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RST_CORE_M, set_bit); + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RST_CORE_M, 0); +} + +/**************************************************************************** + * Name: esp32c3_lowputc_enable_sclk + * Enable clock for whole core + ****************************************************************************/ + +void esp32c3_lowputc_enable_sclk(const struct esp32c3_uart_s *conf) +{ + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_EN_M, + 1 << UART_SCLK_EN_S); + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RX_SCLK_EN_M, + 1 << UART_RX_SCLK_EN_S); + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_TX_SCLK_EN_M, + 1 << UART_TX_SCLK_EN_S); +} + +/**************************************************************************** + * Name: esp32c3_lowputc_disable_sclk + * Disable clock for whole core + ****************************************************************************/ + +void esp32c3_lowputc_disable_sclk(const struct esp32c3_uart_s *conf) +{ + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_EN_M, 0); + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RX_SCLK_EN_M, 0); + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_TX_SCLK_EN_M, 0); +} + +/**************************************************************************** + * Name: esp32c3_lowputc_set_sclk + * Set a source clock for UART + * APB_CLK = 1 80 MHz + * CLK_8 = 2 8 MHz + * XTAL_CLK = 3 + ****************************************************************************/ + +void esp32c3_lowputc_set_sclk(const struct esp32c3_uart_s *conf, enum + uart_sclk source) +{ + uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S; + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_SEL_M, clk); +} + +/**************************************************************************** + * Name: esp32c3_lowputc_get_sclk + * Get the source clock for UART + ****************************************************************************/ + +uint32_t esp32c3_lowputc_get_sclk(const struct esp32c3_uart_s * conf) +{ + uint32_t clk_conf_reg; + uint32_t ret = -ENODATA; + clk_conf_reg = getreg32(UART_CLK_CONF_REG(conf->id)); + clk_conf_reg &= UART_SCLK_SEL_M; + clk_conf_reg >>= UART_SCLK_SEL_S; + switch (clk_conf_reg) + { + case 1: + ret = APB_CLK_FREQ; + break; + case 2: + ret = RTC_CLK_FREQ; + break; + case 3: + ret = XTAL_CLK_FREQ; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_lowputc_baud + * Set the baud rate + ****************************************************************************/ + +void esp32c3_lowputc_baud(const struct esp32c3_uart_s * conf) +{ + const int sclk_div = 1; + uint32_t sclk_freq = esp32c3_lowputc_get_sclk(conf); + uint32_t clk_div = ((sclk_freq) << 4) / conf->baud; + uint32_t int_part = clk_div >> 4; + uint32_t frag_part = clk_div & 0xf; + + /* The baud rate configuration register is divided into + * an integer part and a fractional part. + */ + + modifyreg32(UART_CLKDIV_REG(conf->id), UART_CLKDIV_M, int_part); + modifyreg32(UART_CLKDIV_REG(conf->id), UART_CLKDIV_FRAG_M, + frag_part << UART_CLKDIV_FRAG_S); + modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_DIV_NUM_M, + (sclk_div - 1) << UART_SCLK_DIV_NUM_S); +} + +/**************************************************************************** + * Name: esp32c3_lowputc_normal_mode + * Set the UART to operate in normal mode + ****************************************************************************/ + +void esp32c3_lowputc_normal_mode(const struct esp32c3_uart_s * conf) +{ + /* Disable RS485 mode */ + + modifyreg32(UART_RS485_CONF_REG(conf->id), UART_RS485_EN_M, 0); + modifyreg32(UART_RS485_CONF_REG(conf->id), UART_RS485TX_RX_EN_M, 0); + modifyreg32(UART_RS485_CONF_REG(conf->id), UART_RS485RXBY_TX_EN_M, 0); + + /* Disable IRDA mode */ + + modifyreg32(UART_CONF0_REG(conf->id), UART_IRDA_EN_M, 0); +} + +/**************************************************************************** + * Name: esp32c3_lowputc_parity + * Set the parity + ****************************************************************************/ + +void esp32c3_lowputc_parity(const struct esp32c3_uart_s * conf) +{ + if (conf->parity == UART_PARITY_DISABLE) + { + modifyreg32(UART_CONF0_REG(conf->id), UART_PARITY_EN_M, 0); + } + else + { + modifyreg32(UART_CONF0_REG(conf->id), UART_PARITY_M, + ((conf->parity & 0x1) << UART_PARITY_S)); + modifyreg32(UART_CONF0_REG(conf->id), UART_PARITY_EN_M, + 1 << UART_PARITY_EN_S); + } +} + +/**************************************************************************** + * Name: esp32c3_lowputc_data_length + * Set the data length + ****************************************************************************/ + +int esp32c3_lowputc_data_length(const struct esp32c3_uart_s * conf) +{ + int ret = OK; + uint32_t length = (conf->bits - 5); + + /* If it is the allowed range */ + + if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS) + { + modifyreg32(UART_CONF0_REG(conf->id), UART_BIT_NUM_M, + length << UART_BIT_NUM_S); + } + else + { + ret = -EINVAL; + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_lowputc_stop_length + * Set the stop length + ****************************************************************************/ + +void esp32c3_lowputc_stop_length(const struct esp32c3_uart_s * conf) +{ + if (conf->stop_b2 == 0) + { + modifyreg32(UART_CONF0_REG(conf->id), UART_STOP_BIT_NUM_M, + UART_STOP_BITS_1 << UART_STOP_BIT_NUM_S); + } + else + { + modifyreg32(UART_CONF0_REG(conf->id), UART_STOP_BIT_NUM_M, + UART_STOP_BITS_2 << UART_STOP_BIT_NUM_S); + } +} + +/**************************************************************************** + * Name: esp32c3_lowputc_set_tx_idle_time + * Set the idle time between transfers + ****************************************************************************/ + +void esp32c3_lowputc_set_tx_idle_time(const struct esp32c3_uart_s * + conf, uint32_t time) +{ + time = time << UART_TX_IDLE_NUM_S; + time = time & UART_TX_IDLE_NUM_M; /* Just in case value overloads */ + modifyreg32(UART_IDLE_CONF_REG(conf->id), UART_TX_IDLE_NUM_M, + time); +} + +/**************************************************************************** + * Name: esp32c3_lowputc_send_byte + * Send one byte + ****************************************************************************/ + +void esp32c3_lowputc_send_byte(const struct esp32c3_uart_s * conf, + char byte) +{ + putreg32((uint32_t) byte, UART_FIFO_REG(conf->id)); +} + +/**************************************************************************** + * Name: esp32c3_lowputc_is_tx_fifo_full + * Verifies if TX FIFO is full + ****************************************************************************/ + +bool esp32c3_lowputc_is_tx_fifo_full(const struct esp32c3_uart_s * + conf) +{ + uint32_t reg; + reg = getreg32(UART_STATUS_REG(conf->id)); + reg = reg >> UART_TXFIFO_CNT_S; + reg = reg & UART_TXFIFO_CNT_V; + if (reg < (UART_TX_FIFO_SIZE -1)) + { + return false; + } + else + { + return true; + } +} + +/**************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + + /* Wait until the TX FIFO has space to insert new char */ + + while (esp32c3_lowputc_is_tx_fifo_full(&g_console_config)); + + /* Then send the character */ + + esp32c3_lowputc_send_byte(&g_console_config, ch); + +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Name: esp32c3_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void esp32c3_lowsetup(void) +{ + /* Enable and configure the selected console device */ + +#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + + /* Configure Clock */ + + /* esp32c3_lowputc_set_sclk(&g_console_config, APB_CLK); */ + + /* Configure the UART Baud Rate */ + + /* esp32c3_lowputc_baud(&g_console_config); */ + + /* Set a mode */ + + esp32c3_lowputc_normal_mode(&g_console_config); + + /* Parity */ + + esp32c3_lowputc_parity(&g_console_config); + + /* Data Frame size */ + + esp32c3_lowputc_data_length(&g_console_config); + + /* Stop bit */ + + esp32c3_lowputc_stop_length(&g_console_config); + + /* No Tx idle interval */ + + esp32c3_lowputc_set_tx_idle_time(&g_console_config, 0); + + /* Enable cores */ + + esp32c3_lowputc_enable_sclk(&g_console_config); + +#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_lowputc.h b/arch/risc-v/src/esp32c3/esp32c3_lowputc.h new file mode 100644 index 0000000000..4adec9d70d --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_lowputc.h @@ -0,0 +1,207 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "hardware/esp32c3_uart.h" +#include "chip.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum uart_sclk +{ + APB_CLK = 1, /* 80 MHz */ + CLK_8, /* 8 MHz */ + XTAL_CLK +}; + +enum uart_parity +{ + UART_PARITY_DISABLE, + UART_PARITY_ODD, + UART_PARITY_EVEN +}; + +enum uart_data_length +{ + UART_DATA_5_BITS, + UART_DATA_6_BITS, + UART_DATA_7_BITS, + UART_DATA_8_BITS +}; + +enum uart_stop_length +{ + UART_STOP_BITS_1 = 0x1, /* stop bit: 1 bit */ + UART_STOP_BITS_2 = 0x3, /* stop bit: 2bits */ +}; + +/* Default FIFOs size */ + +#define UART_TX_FIFO_SIZE 128 +#define UART_RX_FIFO_SIZE 128 + +/* Struct used to store uart driver information and to + * manipulate uart driver + */ + +struct esp32c3_uart_s +{ + uint32_t base; /* Base address of UART registers */ + uint8_t periph; /* UART peripheral ID */ + int cpuint; /* CPU interrupt assigned to this UART */ + uint8_t id; /* UART ID */ + uint8_t irq; /* IRQ associated with this UART */ + uint32_t baud; /* Configured baud rate */ + uint8_t bits; + uint8_t parity; /* 0=no parity, 1=odd parity, 2=even parity */ + uint8_t stop_b2; /* Use 2 stop bits? 0 no, others yes */ + uint8_t int_pri; /* UART Interrupt Priority */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_lowputc_reset_core + * Reset both TX and RX core + ****************************************************************************/ + +void esp32c3_lowputc_reset_core(const struct esp32c3_uart_s *conf); + +/**************************************************************************** + * Name: esp32c3_lowputc_enable_sclk + * Enable clock for whole core + ****************************************************************************/ + +void esp32c3_lowputc_enable_sclk(const struct esp32c3_uart_s *conf); + +/**************************************************************************** + * Name: esp32c3_lowputc_disable_sclk + * Disable clock for whole core + ****************************************************************************/ + +void esp32c3_lowputc_disable_sclk(const struct esp32c3_uart_s *conf); + +/**************************************************************************** + * Name: esp32c3_lowputc_set_sclk + * Set a source clock for UART + * APB_CLK = 1 80 MHz + * CLK_8 = 2 8 MHz + * XTAL_CLK = 3 + ****************************************************************************/ + +void esp32c3_lowputc_set_sclk(const struct esp32c3_uart_s *conf, enum + uart_sclk source); + +/**************************************************************************** + * Name: esp32c3_lowputc_get_sclk + * Get the source clock for UART + ****************************************************************************/ + +uint32_t esp32c3_lowputc_get_sclk(const struct esp32c3_uart_s *conf); + +/**************************************************************************** + * Name: esp32c3_lowputc_baud + * Set the baud rate + ****************************************************************************/ + +void esp32c3_lowputc_baud(const struct esp32c3_uart_s * conf); + +/**************************************************************************** + * Name: esp32c3_lowputc_normal_mode + * Set the UART to operate in normal mode + ****************************************************************************/ + +void esp32c3_lowputc_normal_mode(const struct esp32c3_uart_s * conf); + +/**************************************************************************** + * Name: esp32c3_lowputc_parity + * Set the parity + ****************************************************************************/ + +void esp32c3_lowputc_parity(const struct esp32c3_uart_s * conf); + +/**************************************************************************** + * Name: esp32c3_lowputc_data_length + * Set the data length + ****************************************************************************/ + +int esp32c3_lowputc_data_length(const struct esp32c3_uart_s * conf); + +/**************************************************************************** + * Name: esp32c3_lowputc_stop_length + * Set the stop length + ****************************************************************************/ + +void esp32c3_lowputc_stop_length(const struct esp32c3_uart_s * conf); + +/**************************************************************************** + * Name: esp32c3_lowputc_set_tx_idle_time + * Set the idle time between transfers + ****************************************************************************/ + +void esp32c3_lowputc_set_tx_idle_time(const struct esp32c3_uart_s * + conf, uint32_t time); + +/**************************************************************************** + * Name: esp32c3_lowputc_send_byte + * Send one byte + ****************************************************************************/ + +void esp32c3_lowputc_send_byte(const struct esp32c3_uart_s * conf, + char byte); + +/**************************************************************************** + * Name: esp32c3_lowputc_is_tx_fifo_full + * Send one byte + ****************************************************************************/ + +bool esp32c3_lowputc_is_tx_fifo_full(const struct esp32c3_uart_s * + conf); + +/**************************************************************************** + * Name: esp32c3_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void esp32c3_lowsetup(void); diff --git a/arch/risc-v/src/esp32c3/esp32c3_serial.c b/arch/risc-v/src/esp32c3/esp32c3_serial.c new file mode 100644 index 0000000000..9f5ae7219e --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_serial.c @@ -0,0 +1,696 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "hardware/esp32c3_uart.h" +#include "riscv_internal.h" +#include "riscv_arch.h" +#include "chip.h" +#include "esp32c3_lowputc.h" +#include "esp32c3_config.h" +#include "esp32c3_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The console is enabled, and it's not the syslog device, + * so, it should be a serial device. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? */ + +/* First pick the console and ttys0. + * Console can be UART0 or UART1, but will always be ttys0. + */ + +/* In case a UART was assigned to be + * the console and the corresponding peripheral was also selected. + */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0_dev /* UART0 is console */ +# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1_dev /* UART1 is console */ +# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# endif /* CONFIG_UART0_SERIAL_CONSOLE */ +#else /* No console */ +# undef CONSOLE_DEV +# if defined(CONFIG_ESP32C3_UART0) +# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_ESP32C3_UART1) +# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# endif +#endif /* HAVE_SERIAL_CONSOLE */ + +/* Pick ttys1 */ + +#if defined(CONFIG_ESP32C3_UART0) && !defined(UART0_ASSIGNED) +# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_ESP32C3_UART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#endif + +#ifdef HAVE_UART_DEVICE + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Serial driver methods */ + +static int esp32c3_setup(struct uart_dev_s *dev); +static void esp32c3_shutdown(struct uart_dev_s *dev); +static int esp32c3_attach(struct uart_dev_s *dev); +static void esp32c3_detach(struct uart_dev_s *dev); +static void esp32c3_txint(struct uart_dev_s *dev, bool enable); +static void esp32c3_rxint(struct uart_dev_s *dev, bool enable); +static bool esp32c3_rxavailable(struct uart_dev_s *dev); +static bool esp32c3_txready(struct uart_dev_s *dev); +static bool esp32c3_txempty(struct uart_dev_s *dev); +static void esp32c3_send(struct uart_dev_s *dev, int ch); +static int esp32c3_receive(struct uart_dev_s *dev, unsigned int *status); +static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Operations */ + +static struct uart_ops_s g_uart_ops = +{ + .setup = esp32c3_setup, + .shutdown = esp32c3_shutdown, + .attach = esp32c3_attach, + .detach = esp32c3_detach, + .txint = esp32c3_txint, + .rxint = esp32c3_rxint, + .rxavailable = esp32c3_rxavailable, + .txready = esp32c3_txready, + .txempty = esp32c3_txempty, + .send = esp32c3_send, + .receive = esp32c3_receive, + .ioctl = esp32c3_ioctl, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif +}; + +/* UART 0 */ + +#ifdef CONFIG_ESP32C3_UART0 + +static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE]; + +static struct esp32c3_uart_s g_uart0_config = +{ + .base = REG_UART_BASE(0), + .periph = ESP32C3_PERIPH_UART0, + .id = 0, + .irq = ESP32C3_IRQ_UART0, + .baud = CONFIG_UART0_BAUD, + .bits = CONFIG_UART0_BITS, + .parity = CONFIG_UART0_PARITY, + .stop_b2 = CONFIG_UART0_2STOP, + .int_pri = 1 +}; + +/* Fill only the requested fields */ + +static uart_dev_t g_uart0_dev = +{ +#ifdef CONFIG_UART0_SERIAL_CONSOLE + .isconsole = true, +#else + .isconsole = false, +#endif + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0_txbuffer, + }, + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0_rxbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart0_config +}; + +#endif + +/* UART 1 */ + +#ifdef CONFIG_ESP32C3_UART1 + +static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; + +static struct esp32c3_uart_s g_uart1_config = +{ + .base = REG_UART_BASE(1), + .periph = ESP32C3_PERIPH_UART1, + .id = 1, + .irq = ESP32C3_IRQ_UART1, + .baud = CONFIG_UART1_BAUD, + .bits = CONFIG_UART1_BITS, + .parity = CONFIG_UART1_PARITY, + .stop_b2 = CONFIG_UART1_2STOP, + .int_pri = 1 +}; + +/* Fill only the requested fields */ + +static uart_dev_t g_uart1_dev = +{ +#ifdef CONFIG_UART1_SERIAL_CONSOLE + .isconsole = true, +#else + .isconsole = false, +#endif + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1_txbuffer, + }, + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1_rxbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart1_config +}; + +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: uart_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int uart_handler(int irq, FAR void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct esp32c3_uart_s *priv = dev->priv; + uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M; + uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M; + uint32_t int_status; + + int_status = getreg32(UART_INT_ST_REG(priv->id)); + + /* Tx fifo empty interrupt or UART tx done int */ + + if (int_status & tx_mask) + { + uart_xmitchars(dev); + modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask); + } + + /* Rx fifo timeout interrupt or rx fifo full interrupt */ + + if (int_status & rx_mask) + { + uart_recvchars(dev); + modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This method is + * called the first time that the serial port is opened. + * For the serial console, this will occur very early in initialization, + * for other serial ports this will occur when the port is first opened. + * This setup does not include attaching or enabling interrupts. + * That portion of the UART setup is performed when the attach() method + * is called. + * + ****************************************************************************/ + +static int esp32c3_setup(struct uart_dev_s *dev) +{ + return OK; +} + +/**************************************************************************** + * Name: esp32c3_shutdown + * + * Description: + * Disable the UART. This method is called when the serial port is closed. + * This method reverses the operation the setup method. NOTE that the serial + * console is never shutdown. + * + ****************************************************************************/ + +static void esp32c3_shutdown(struct uart_dev_s *dev) +{ +} + +/**************************************************************************** + * Name: esp32c3_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the the setup() method is called, however, the serial console may + * operate in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int esp32c3_attach(struct uart_dev_s *dev) +{ + struct esp32c3_uart_s *priv = dev->priv; + int ret; + + /* Try to attach the IRQ to a CPU int */ + + priv->cpuint = esp32c3_request_irq(priv->periph, priv->int_pri, + ESP32C3_INT_LEVEL); + if (priv->cpuint < 0) + { + return priv->cpuint; + } + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, uart_handler, dev); + if (ret == OK) + { + up_enable_irq(priv->cpuint); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void esp32c3_detach(struct uart_dev_s *dev) +{ + struct esp32c3_uart_s *priv = dev->priv; + + up_disable_irq(priv->cpuint); + irq_detach(priv->irq); + esp32c3_free_cpuint(priv->periph); +} + +/**************************************************************************** + * Name: esp32c3_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void esp32c3_txint(struct uart_dev_s *dev, bool enable) +{ + struct esp32c3_uart_s *priv = dev->priv; + irqstate_t flags; + uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M; + + flags = enter_critical_section(); + + if (enable) + { + /* Set to receive an interrupt when the TX holding register register + * is empty + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask); +#endif + } + else + { + /* Disable the TX interrupt */ + + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32c3_rxint + * + * Description: + * Call to enable or disable RXRDY interrupts + * + ****************************************************************************/ + +static void esp32c3_rxint(struct uart_dev_s *dev, bool enable) +{ + struct esp32c3_uart_s *priv = dev->priv; + irqstate_t flags; + uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M | + UART_RXFIFO_FULL_INT_ENA_M; + + flags = enter_critical_section(); + + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register + * (or an Rx timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask); +#endif + } + else + { + /* Disable the RX interrupts */ + + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32c3_rxavailable + * + * Description: + * Return true if the receive holding register is not empty + * + ****************************************************************************/ + +static bool esp32c3_rxavailable(struct uart_dev_s *dev) +{ + struct esp32c3_uart_s *priv = dev->priv; + uint32_t status_reg; + uint32_t bytes; + + status_reg = getreg32(UART_STATUS_REG(priv->id)); + bytes = status_reg & UART_RXFIFO_CNT_M; + + return (bytes > 0) ? true : false; +} + +/**************************************************************************** + * Name: esp32c3_txready + * + * Description: + * Return true if the tranmsit hardware is ready to send another byte. This + * is used to determine if send() method can be called. + * + ****************************************************************************/ + +static bool esp32c3_txready(struct uart_dev_s *dev) +{ + return (esp32c3_lowputc_is_tx_fifo_full(dev->priv)) ? false : true; +} + +/**************************************************************************** + * Name: esp32c3_txempty + * + * Description: + * Return true if all characters have been sent. If for example, the UART + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware. + * + ****************************************************************************/ + +static bool esp32c3_txempty(struct uart_dev_s *dev) +{ + uint32_t reg; + struct esp32c3_uart_s *priv = dev->priv; + + reg = getreg32(UART_INT_RAW_REG(priv->id)); + reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M; + + return (reg > 0) ? true : false; +} + +/**************************************************************************** + * Name: esp32c3_shutdown + * + * Description: + * Disable the UART. This method is called when the serial port is closed. + * This method reverses the operation the setup method. NOTE that the serial + * console is never shutdown. + * + ****************************************************************************/ + +static void esp32c3_send(struct uart_dev_s *dev, int ch) +{ + /* Then send the character */ + + esp32c3_lowputc_send_byte(dev->priv, ch); +} + +/**************************************************************************** + * Name: esp32c3_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int esp32c3_receive(struct uart_dev_s *dev, unsigned int *status) +{ + uint32_t rx_fifo; + struct esp32c3_uart_s *priv = dev->priv; + + rx_fifo = getreg32(UART_FIFO_REG(priv->id)); + rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M; + + return (int)rx_fifo; +} + +static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT + +/**************************************************************************** + * Name: up_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock + * initialization performed in up_clkinitialize(). + * + ****************************************************************************/ + +/* TODO */ + +void up_earlyserialinit(void) +{ + /* I've been looking at others chips/arches and I noticed + * that _lowsetup performs almost the same of this func and it's + * called earlier than this one in _start + * So, I am not sure what to do here + */ +} + +#endif /* USE_EARLYSERIALINIT */ + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +/* TODO */ + +void up_serialinit(void) +{ +#ifdef HAVE_SERIAL_CONSOLE + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* At least one UART char driver will logically be registered */ + + uart_register("/dev/ttyS0", &TTYS0_DEV); + +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +/* TODO - To finish later with interrupt */ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + + /* TODO disable uart ints */ + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + + /* TODO restore ints */ +#endif + return ch; +} + +#else /* HAVE_UART_DEVICE */ + +/**************************************************************************** + * Name: up_earlyserialinit, up_serialinit, and up_putc + * + * Description: + * stubs that may be needed. These stubs will be used if all UARTs are + * disabled. In that case, the logic in common/up_initialize() is not + * smart enough to know that there are not UARTs and will still expect + * these interfaces to be provided. + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ +} + +void up_serialinit(void) +{ +} + +int up_putc(int ch) +{ + return ch; +} + +#endif /* HAVE_UART_DEVICE */ +#else /* USE_SERIALDRIVER */ + +/* Common initialization logic will not not know that the all of the UARTs + * have been disabled. So, as a result, we may still have to provide + * stub implementations of up_earlyserialinit(), up_serialinit(), and + * up_putc(). + */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +/* TODO - Finish it disabling interrupt and restoring it later */ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_start.c b/arch/risc-v/src/esp32c3/esp32c3_start.c index 413f93389d..df89e3c7d6 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_start.c +++ b/arch/risc-v/src/esp32c3/esp32c3_start.c @@ -32,13 +32,14 @@ #include "chip.h" #include "esp32c3.h" #include "esp32c3_irq.h" +#include "esp32c3_lowputc.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -# define showprogress(c) ets_printf("%c", c) +# define showprogress(c) up_lowputc(c) #else # define showprogress(c) #endif @@ -65,6 +66,10 @@ void __esp32c3_start(void) { uint32_t *dest; + /* Configure the UART so we can get debug output */ + + esp32c3_lowsetup(); + showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -82,7 +87,5 @@ void __esp32c3_start(void) nx_start(); - /* Shouldn't get here */ - for (; ; ); } diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h index 8fe1f834bc..44114f2682 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h @@ -73,6 +73,8 @@ #define DR_REG_APB_SARADC_BASE 0x60040000 #define DR_REG_AES_XTS_BASE 0x600CC000 +/* Registers Operation */ + #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + \ ( (i) > 1 ? 0xe000 : 0 ) ) diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h new file mode 100644 index 0000000000..0b8abc0759 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h @@ -0,0 +1,2185 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_UART_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_memorymap.h" +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* FIFO Configuration */ + +/* UART_FIFO_REG register + * FIFO data + * register + */ + +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) + +/* UART_RXFIFO_RD_BYTE : RO; bitpos: [8:0]; default: 0; + * UART $n accesses FIFO via this + * register. + */ + +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FF +#define UART_RXFIFO_RD_BYTE_S 0 + +/* UART_MEM_CONF_REG register + * UART threshold and allocation + * configuration + */ + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) + +/* UART_RX_SIZE : R/W; bitpos: [4:1]; default: 1; + * This register is used to configure the amount of mem allocated for + * receive-FIFO. The default number is 128 + * bytes. + */ + +#define UART_RX_SIZE 0x00000007 +#define UART_RX_SIZE_M (UART_RX_SIZE_V << UART_RX_SIZE_S) +#define UART_RX_SIZE_V 0x00000007 +#define UART_RX_SIZE_S 1 + +/* UART_TX_SIZE : R/W; bitpos: [7:4]; default: 1; + * This register is used to configure the amount of mem allocated for + * transmit-FIFO. The default number is 128 + * bytes. + */ + +#define UART_TX_SIZE 0x00000007 +#define UART_TX_SIZE_M (UART_TX_SIZE_V << UART_TX_SIZE_S) +#define UART_TX_SIZE_V 0x00000007 +#define UART_TX_SIZE_S 4 + +/* UART_RX_FLOW_THRHD : R/W; bitpos: [16:7]; default: 0; + * This register is used to configure the maximum amount of data that can + * be received when hardware flow control + * works. + */ + +#define UART_RX_FLOW_THRHD 0x000001FF +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000001FF +#define UART_RX_FLOW_THRHD_S 7 + +/* UART_RX_TOUT_THRHD : R/W; bitpos: [26:16]; default: 10; + * This register is used to configure the threshold time that receiver + * takes to receive one byte. The rxfifo_tout_int interrupt will be + * trigger when the receiver takes more time to receive one byte with + * rx_tout_en set to + * 1. + */ + +#define UART_RX_TOUT_THRHD 0x000003FF +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FF +#define UART_RX_TOUT_THRHD_S 16 + +/* UART_MEM_FORCE_PD : R/W; bitpos: [26]; default: 0; + * Set this bit to force power down UART + * memory. + */ + +#define UART_MEM_FORCE_PD (BIT(26)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001 +#define UART_MEM_FORCE_PD_S 26 + +/* UART_MEM_FORCE_PU : R/W; bitpos: [27]; default: 0; + * Set this bit to force power up UART + * memory. + */ + +#define UART_MEM_FORCE_PU (BIT(27)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001 +#define UART_MEM_FORCE_PU_S 27 + +/* Interrupt Register */ + +/* UART_INT_RAW_REG register + * Raw interrupt + * status + */ + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) + +/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more + * data than what rxfifo_full_thrhd + * specifies. + */ + +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in + * Tx-FIFO is less than what txfifo_empty_thrhd specifies + * . + */ + +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 + +/* UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a + * parity error in the + * data. + */ + +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001 +#define UART_PARITY_ERR_INT_RAW_S 2 + +/* UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data + * frame error + * . + */ + +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001 +#define UART_FRM_ERR_INT_RAW_S 3 + +/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more + * data than the FIFO can + * store. + */ + +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001 +#define UART_RXFIFO_OVF_INT_RAW_S 4 + +/* UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the + * edge change of DSRn + * signal. + */ + +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001 +#define UART_DSR_CHG_INT_RAW_S 5 + +/* UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the + * edge change of CTSn + * signal. + */ + +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001 +#define UART_CTS_CHG_INT_RAW_S 6 + +/* UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 + * after the stop + * bit. + */ + +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001 +#define UART_BRK_DET_INT_RAW_S 7 + +/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more + * time than rx_tout_thrhd to receive a + * byte. + */ + +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 + +/* UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon + * char when uart_sw_flow_con_en is set to + * 1. + */ + +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001 +#define UART_SW_XON_INT_RAW_S 9 + +/* UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff + * char when uart_sw_flow_con_en is set to + * 1. + */ + +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001 +#define UART_SW_XOFF_INT_RAW_S 10 + +/* UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a + * glitch in the middle of a start + * bit. + */ + +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001 +#define UART_GLITCH_DET_INT_RAW_S 11 + +/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes + * sending NULL characters, after all data in Tx-FIFO are + * sent. + */ + +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001 +#define UART_TX_BRK_DONE_INT_RAW_S 12 + +/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept + * the shortest duration after sending the last + * data. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 + +/* UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send + * out all data in + * FIFO. + */ + +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001 +#define UART_TX_DONE_INT_RAW_S 14 + +/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a + * parity error from the echo of transmitter in rs485 + * mode. + */ + +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 + +/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data + * frame error from the echo of transmitter in rs485 + * mode. + */ + +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 + +/* UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between + * transmitter and receiver in rs485 + * mode. + */ + +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001 +#define UART_RS485_CLASH_INT_RAW_S 17 + +/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the + * configured at_cmd + * char. + */ + +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 + +/* UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes + * more times than what reg_active_threshold specifies in light sleeping + * mode. + */ + +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001 +#define UART_WAKEUP_INT_RAW_S 19 + +/* UART_INT_ST_REG register + * Masked interrupt + * status + */ + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) + +/* UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena + * is set to + * 1. + */ + +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +/* UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when + * txfifo_empty_int_ena is set to + * 1. + */ + +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 + +/* UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena + * is set to + * 1. + */ + +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001 +#define UART_PARITY_ERR_INT_ST_S 2 + +/* UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set + * to + * 1. + */ + +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001 +#define UART_FRM_ERR_INT_ST_S 3 + +/* UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena + * is set to + * 1. + */ + +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001 +#define UART_RXFIFO_OVF_INT_ST_S 4 + +/* UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set + * to + * 1. + */ + +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001 +#define UART_DSR_CHG_INT_ST_S 5 + +/* UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set + * to + * 1. + */ + +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001 +#define UART_CTS_CHG_INT_ST_S 6 + +/* UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set + * to + * 1. + */ + +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001 +#define UART_BRK_DET_INT_ST_S 7 + +/* UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena + * is set to + * 1. + */ + +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_ST_S 8 + +/* UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to + * 1. + */ + +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001 +#define UART_SW_XON_INT_ST_S 9 + +/* UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set + * to + * 1. + */ + +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001 +#define UART_SW_XOFF_INT_ST_S 10 + +/* UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena + * is set to + * 1. + */ + +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001 +#define UART_GLITCH_DET_INT_ST_S 11 + +/* UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena + * is set to + * 1. + */ + +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001 +#define UART_TX_BRK_DONE_INT_ST_S 12 + +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when + * tx_brk_idle_done_int_ena is set to + * 1. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 + +/* UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set + * to + * 1. + */ + +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001 +#define UART_TX_DONE_INT_ST_S 14 + +/* UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when + * rs485_parity_int_ena is set to + * 1. + */ + +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 + +/* UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when + * rs485_fm_err_int_ena is set to + * 1. + */ + +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_ST_S 16 + +/* UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena + * is set to + * 1. + */ + +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001 +#define UART_RS485_CLASH_INT_ST_S 17 + +/* UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when + * at_cmd_char_det_int_ena is set to + * 1. + */ + +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 + +/* UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena + * is set to + * 1. + */ + +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001 +#define UART_WAKEUP_INT_ST_S 19 + +/* UART_INT_ENA_REG register + * Interrupt enable + * bits + */ + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) + +/* UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st + * register. + */ + +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +/* UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st + * register. + */ + +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 + +/* UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st + * register. + */ + +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001 +#define UART_PARITY_ERR_INT_ENA_S 2 + +/* UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st + * register. + */ + +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001 +#define UART_FRM_ERR_INT_ENA_S 3 + +/* UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st + * register. + */ + +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001 +#define UART_RXFIFO_OVF_INT_ENA_S 4 + +/* UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st + * register. + */ + +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001 +#define UART_DSR_CHG_INT_ENA_S 5 + +/* UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st + * register. + */ + +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001 +#define UART_CTS_CHG_INT_ENA_S 6 + +/* UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st + * register. + */ + +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001 +#define UART_BRK_DET_INT_ENA_S 7 + +/* UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st + * register. + */ + +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 + +/* UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st + * register. + */ + +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001 +#define UART_SW_XON_INT_ENA_S 9 + +/* UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st + * register. + */ + +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001 +#define UART_SW_XOFF_INT_ENA_S 10 + +/* UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st + * register. + */ + +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001 +#define UART_GLITCH_DET_INT_ENA_S 11 + +/* UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st + * register. + */ + +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001 +#define UART_TX_BRK_DONE_INT_ENA_S 12 + +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st + * register. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 + +/* UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st + * register. + */ + +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001 +#define UART_TX_DONE_INT_ENA_S 14 + +/* UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st + * register. + */ + +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 + +/* UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st + * register. + */ + +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 + +/* UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st + * register. + */ + +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001 +#define UART_RS485_CLASH_INT_ENA_S 17 + +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st + * register. + */ + +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 + +/* UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st + * register. + */ + +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001 +#define UART_WAKEUP_INT_ENA_S 19 + +/* UART_INT_CLR_REG register + * Interrupt clear + * bits + */ + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) + +/* UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw + * interrupt. + */ + +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +/* UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw + * interrupt. + */ + +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 + +/* UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw + * interrupt. + */ + +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001 +#define UART_PARITY_ERR_INT_CLR_S 2 + +/* UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw + * interrupt. + */ + +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001 +#define UART_FRM_ERR_INT_CLR_S 3 + +/* UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw + * interrupt. + */ + +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001 +#define UART_RXFIFO_OVF_INT_CLR_S 4 + +/* UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw + * interrupt. + */ + +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001 +#define UART_DSR_CHG_INT_CLR_S 5 + +/* UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw + * interrupt. + */ + +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001 +#define UART_CTS_CHG_INT_CLR_S 6 + +/* UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw + * interrupt. + */ + +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001 +#define UART_BRK_DET_INT_CLR_S 7 + +/* UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw + * interrupt. + */ + +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 + +/* UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw + * interrupt. + */ + +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001 +#define UART_SW_XON_INT_CLR_S 9 + +/* UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw + * interrupt. + */ + +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001 +#define UART_SW_XOFF_INT_CLR_S 10 + +/* UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw + * interrupt. + */ + +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001 +#define UART_GLITCH_DET_INT_CLR_S 11 + +/* UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw + * interrupt.. + */ + +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001 +#define UART_TX_BRK_DONE_INT_CLR_S 12 + +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw + * interrupt. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 + +/* UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw + * interrupt. + */ + +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001 +#define UART_TX_DONE_INT_CLR_S 14 + +/* UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw + * interrupt. + */ + +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 + +/* UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw + * interrupt. + */ + +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 + +/* UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw + * interrupt. + */ + +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001 +#define UART_RS485_CLASH_INT_CLR_S 17 + +/* UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw + * interrupt. + */ + +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 + +/* UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw + * interrupt. + */ + +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001 +#define UART_WAKEUP_INT_CLR_S 19 + +/* Configuration Register */ + +/* UART_CLKDIV_REG register + * Clock divider + * configuration + */ + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) + +/* UART_CLKDIV : R/W; bitpos: [12:0]; default: 694; + * The integral part of the frequency divider + * factor. + */ + +#define UART_CLKDIV 0x00000FFF +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x00000FFF +#define UART_CLKDIV_S 0 + +/* UART_CLKDIV_FRAG : R/W; bitpos: [24:20]; default: 0; + * The decimal part of the frequency divider + * factor. + */ + +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000F +#define UART_CLKDIV_FRAG_S 20 + +/* UART_RX_FILT_REG register + * Rx Filter + * configuration + */ + +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) + +/* UART_GLITCH_FILT : R/W; bitpos: [8:0]; default: 8; + * when input pulse width is lower than this value, the pulse is + * ignored. + */ + +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FF +#define UART_GLITCH_FILT_S 0 + +/* UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal + * filter. + */ + +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) +#define UART_GLITCH_FILT_EN_V 0x00000001 +#define UART_GLITCH_FILT_EN_S 8 + +/* UART_CONF0_REG register + * a + */ + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) + +/* UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check + * mode. + */ + +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001 +#define UART_PARITY_S 0 + +/* UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity + * check. + */ + +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001 +#define UART_PARITY_EN_S 1 + +/* UART_BIT_NUM : R/W; bitpos: [4:2]; default: 3; + * This register is used to set the length of + * data. + */ + +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003 +#define UART_BIT_NUM_S 2 + +/* UART_STOP_BIT_NUM : R/W; bitpos: [6:4]; default: 1; + * This register is used to set the length of stop + * bit. + */ + +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003 +#define UART_STOP_BIT_NUM_S 4 + +/* UART_SW_RTS : R/W; bitpos: [6]; default: 0; + * This register is used to configure the software rts signal which is + * used in software flow + * control. + */ + +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001 +#define UART_SW_RTS_S 6 + +/* UART_SW_DTR : R/W; bitpos: [7]; default: 0; + * This register is used to configure the software dtr signal which is + * used in software flow + * control. + */ + +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001 +#define UART_SW_DTR_S 7 + +/* UART_TXD_BRK : R/W; bitpos: [8]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of + * sending data is + * done. + */ + +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001 +#define UART_TXD_BRK_S 8 + +/* UART_IRDA_DPLX : R/W; bitpos: [9]; default: 0; + * Set this bit to enable IrDA loopback + * mode. + */ + +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001 +#define UART_IRDA_DPLX_S 9 + +/* UART_IRDA_TX_EN : R/W; bitpos: [10]; default: 0; + * This is the start enable bit for IrDA + * transmitter. + */ + +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001 +#define UART_IRDA_TX_EN_S 10 + +/* UART_IRDA_WCTL : R/W; bitpos: [11]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: + * Set IrDA transmitter's 11th bit to + * 0. + */ + +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001 +#define UART_IRDA_WCTL_S 11 + +/* UART_IRDA_TX_INV : R/W; bitpos: [12]; default: 0; + * Set this bit to invert the level of IrDA + * transmitter. + */ + +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001 +#define UART_IRDA_TX_INV_S 12 + +/* UART_IRDA_RX_INV : R/W; bitpos: [13]; default: 0; + * Set this bit to invert the level of IrDA + * receiver. + */ + +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001 +#define UART_IRDA_RX_INV_S 13 + +/* UART_LOOPBACK : R/W; bitpos: [14]; default: 0; + * Set this bit to enable uart loopback test + * mode. + */ + +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001 +#define UART_LOOPBACK_S 14 + +/* UART_TX_FLOW_EN : R/W; bitpos: [15]; default: 0; + * Set this bit to enable flow control function for + * transmitter. + */ + +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001 +#define UART_TX_FLOW_EN_S 15 + +/* UART_IRDA_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to enable IrDA + * protocol. + */ + +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001 +#define UART_IRDA_EN_S 16 + +/* UART_RXFIFO_RST : R/W; bitpos: [17]; default: 0; + * Set this bit to reset the uart + * receive-FIFO. + */ + +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001 +#define UART_RXFIFO_RST_S 17 + +/* UART_TXFIFO_RST : R/W; bitpos: [18]; default: 0; + * Set this bit to reset the uart + * transmit-FIFO. + */ + +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001 +#define UART_TXFIFO_RST_S 18 + +/* UART_RXD_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart rxd + * signal. + */ + +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001 +#define UART_RXD_INV_S 19 + +/* UART_CTS_INV : R/W; bitpos: [20]; default: 0; + * Set this bit to inverse the level value of uart cts + * signal. + */ + +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001 +#define UART_CTS_INV_S 20 + +/* UART_DSR_INV : R/W; bitpos: [21]; default: 0; + * Set this bit to inverse the level value of uart dsr + * signal. + */ + +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001 +#define UART_DSR_INV_S 21 + +/* UART_TXD_INV : R/W; bitpos: [22]; default: 0; + * Set this bit to inverse the level value of uart txd + * signal. + */ + +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001 +#define UART_TXD_INV_S 22 + +/* UART_RTS_INV : R/W; bitpos: [23]; default: 0; + * Set this bit to inverse the level value of uart rts + * signal. + */ + +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001 +#define UART_RTS_INV_S 23 + +/* UART_DTR_INV : R/W; bitpos: [24]; default: 0; + * Set this bit to inverse the level value of uart dtr + * signal. + */ + +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001 +#define UART_DTR_INV_S 24 + +/* UART_CLK_EN : R/W; bitpos: [25]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when + * application writes + * registers. + */ + +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001 +#define UART_CLK_EN_S 25 + +/* UART_ERR_WR_MASK : R/W; bitpos: [26]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: + * Receiver stores the data even if the received data is + * wrong. + */ + +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001 +#define UART_ERR_WR_MASK_S 26 + +/* UART_AUTOBAUD_EN : R/W; bitpos: [27]; default: 0; + * This is the enable bit for detecting + * baudrate. + */ + +#define UART_AUTOBAUD_EN (BIT(27)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001 +#define UART_AUTOBAUD_EN_S 27 + +/* UART_MEM_CLK_EN : R/W; bitpos: [28]; default: 1; + * UART memory clock gate enable + * signal. + */ + +#define UART_MEM_CLK_EN (BIT(28)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001 +#define UART_MEM_CLK_EN_S 28 + +/* UART_CONF1_REG register + * Configuration register + * 1 + */ + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) + +/* UART_RXFIFO_FULL_THRHD : R/W; bitpos: [9:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more + * data than this register + * value. + */ + +#define UART_RXFIFO_FULL_THRHD 0x000001FF +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000001FF +#define UART_RXFIFO_FULL_THRHD_S 0 + +/* UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [18:9]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in + * Tx-FIFO is less than this register + * value. + */ + +#define UART_TXFIFO_EMPTY_THRHD 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD_S 9 + +/* UART_DIS_RX_DAT_OVF : R/W; bitpos: [18]; default: 0; + * Disable UART Rx data overflow + * detect. + */ + +#define UART_DIS_RX_DAT_OVF (BIT(18)) +#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) +#define UART_DIS_RX_DAT_OVF_V 0x00000001 +#define UART_DIS_RX_DAT_OVF_S 18 + +/* UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [19]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control + * works. + */ + +#define UART_RX_TOUT_FLOW_DIS (BIT(19)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001 +#define UART_RX_TOUT_FLOW_DIS_S 19 + +/* UART_RX_FLOW_EN : R/W; bitpos: [20]; default: 0; + * This is the flow enable bit for UART + * receiver. + */ + +#define UART_RX_FLOW_EN (BIT(20)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001 +#define UART_RX_FLOW_EN_S 20 + +/* UART_RX_TOUT_EN : R/W; bitpos: [21]; default: 0; + * This is the enble bit for uart receiver's timeout + * function. + */ + +#define UART_RX_TOUT_EN (BIT(21)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001 +#define UART_RX_TOUT_EN_S 21 + +/* UART_FLOW_CONF_REG register + * Software flow-control + * configuration + */ + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) + +/* UART_SW_FLOW_CON_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable software flow control. It is used with register + * sw_xon or + * sw_xoff. + */ + +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001 +#define UART_SW_FLOW_CON_EN_S 0 + +/* UART_XONOFF_DEL : R/W; bitpos: [1]; default: 0; + * Set this bit to remove flow control char from the received + * data. + */ + +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001 +#define UART_XONOFF_DEL_S 1 + +/* UART_FORCE_XON : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the transmitter to go on sending + * data. + */ + +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001 +#define UART_FORCE_XON_S 2 + +/* UART_FORCE_XOFF : R/W; bitpos: [3]; default: 0; + * Set this bit to stop the transmitter from sending + * data. + */ + +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001 +#define UART_FORCE_XOFF_S 3 + +/* UART_SEND_XON : R/W/SS/SC; bitpos: [4]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware + * automatically. + */ + +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001 +#define UART_SEND_XON_S 4 + +/* UART_SEND_XOFF : R/W/SS/SC; bitpos: [5]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware + * automatically. + */ + +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001 +#define UART_SEND_XOFF_S 5 + +/* UART_SLEEP_CONF_REG register + * Sleep-mode + * configuration + */ + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) + +/* UART_ACTIVE_THRESHOLD : R/W; bitpos: [10:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge + * changes more times than this register + * value. + */ + +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FF +#define UART_ACTIVE_THRESHOLD_S 0 + +/* UART_SWFC_CONF0_REG register + * Software flow-control character + * configuration + */ + +#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3c) + +/* UART_XOFF_THRESHOLD : R/W; bitpos: [9:0]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1, it will send a Xoff + * char. + */ + +#define UART_XOFF_THRESHOLD 0x000001FF +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000001FF +#define UART_XOFF_THRESHOLD_S 0 + +/* UART_XOFF_CHAR : R/W; bitpos: [17:9]; default: 19; + * This register stores the Xoff flow control + * char. + */ + +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FF +#define UART_XOFF_CHAR_S 9 + +/* UART_SWFC_CONF1_REG register + * Software flow-control character + * configuration + */ + +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) + +/* UART_XON_THRESHOLD : R/W; bitpos: [9:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1, it will send a Xon + * char. + */ + +#define UART_XON_THRESHOLD 0x000001FF +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000001FF +#define UART_XON_THRESHOLD_S 0 + +/* UART_XON_CHAR : R/W; bitpos: [17:9]; default: 17; + * This register stores the Xon flow control + * char. + */ + +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FF +#define UART_XON_CHAR_S 9 + +/* UART_TXBRK_CONF_REG register + * Tx Break character + * configuration + */ + +#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44) + +/* UART_TX_BRK_NUM : R/W; bitpos: [8:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the + * process of sending data is done. It is active when txd_brk is set to + * 1. + */ + +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FF +#define UART_TX_BRK_NUM_S 0 + +/* UART_IDLE_CONF_REG register + * Frame-end idle + * configuration + */ + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48) + +/* UART_RX_IDLE_THRHD : R/W; bitpos: [10:0]; default: 256; + * It will produce frame end signal when receiver takes more time to + * receive one byte data than this register + * value. + */ + +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FF +#define UART_RX_IDLE_THRHD_S 0 + +/* UART_TX_IDLE_NUM : R/W; bitpos: [20:10]; default: 256; + * This register is used to configure the duration time between + * transfers. + */ + +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FF +#define UART_TX_IDLE_NUM_S 10 + +/* UART_RS485_CONF_REG register + * RS485 mode + * configuration + */ + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x4c) + +/* UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 + * mode. + */ + +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001 +#define UART_RS485_EN_S 0 + +/* UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 + * bit. + */ + +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001 +#define UART_DL0_EN_S 1 + +/* UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 + * bit. + */ + +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001 +#define UART_DL1_EN_S 2 + +/* UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter + * is transmitting data in rs485 + * mode. + */ + +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001 +#define UART_RS485TX_RX_EN_S 3 + +/* UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is + * busy. + */ + +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001 +#define UART_RS485RXBY_TX_EN_S 4 + +/* UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data + * signal. + */ + +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001 +#define UART_RS485_RX_DLY_NUM_S 5 + +/* UART_RS485_TX_DLY_NUM : R/W; bitpos: [10:6]; default: 0; + * This register is used to delay the transmitter's internal data + * signal. + */ + +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000F +#define UART_RS485_TX_DLY_NUM_S 6 + +/* UART_CLK_CONF_REG register + * UART core clock + * configuration + */ + +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x78) + +/* UART_SCLK_DIV_B : R/W; bitpos: [6:0]; default: 0; + * The denominator of the frequency divider + * factor. + */ + +#define UART_SCLK_DIV_B 0x0000003F +#define UART_SCLK_DIV_B_M (UART_SCLK_DIV_B_V << UART_SCLK_DIV_B_S) +#define UART_SCLK_DIV_B_V 0x0000003F +#define UART_SCLK_DIV_B_S 0 + +/* UART_SCLK_DIV_A : R/W; bitpos: [12:6]; default: 0; + * The numerator of the frequency divider + * factor. + */ + +#define UART_SCLK_DIV_A 0x0000003F +#define UART_SCLK_DIV_A_M (UART_SCLK_DIV_A_V << UART_SCLK_DIV_A_S) +#define UART_SCLK_DIV_A_V 0x0000003F +#define UART_SCLK_DIV_A_S 6 + +/* UART_SCLK_DIV_NUM : R/W; bitpos: [20:12]; default: 1; + * The integral part of the frequency divider + * factor. + */ + +#define UART_SCLK_DIV_NUM 0x000000FF +#define UART_SCLK_DIV_NUM_M (UART_SCLK_DIV_NUM_V << UART_SCLK_DIV_NUM_S) +#define UART_SCLK_DIV_NUM_V 0x000000FF +#define UART_SCLK_DIV_NUM_S 12 + +/* UART_SCLK_SEL : R/W; bitpos: [22:20]; default: 3; + * UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: + * XTAL. + */ + +#define UART_SCLK_SEL 0x00000003 +#define UART_SCLK_SEL_M (UART_SCLK_SEL_V << UART_SCLK_SEL_S) +#define UART_SCLK_SEL_V 0x00000003 +#define UART_SCLK_SEL_S 20 + +/* UART_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx + * clock. + */ + +#define UART_SCLK_EN (BIT(22)) +#define UART_SCLK_EN_M (UART_SCLK_EN_V << UART_SCLK_EN_S) +#define UART_SCLK_EN_V 0x00000001 +#define UART_SCLK_EN_S 22 + +/* UART_RST_CORE : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit, reset UART + * Tx/Rx. + */ + +#define UART_RST_CORE (BIT(23)) +#define UART_RST_CORE_M (UART_RST_CORE_V << UART_RST_CORE_S) +#define UART_RST_CORE_V 0x00000001 +#define UART_RST_CORE_S 23 + +/* UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx + * clock. + */ + +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) +#define UART_TX_SCLK_EN_V 0x00000001 +#define UART_TX_SCLK_EN_S 24 + +/* UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx + * clock. + */ + +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) +#define UART_RX_SCLK_EN_V 0x00000001 +#define UART_RX_SCLK_EN_S 25 + +/* UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit, reset UART + * Tx. + */ + +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) +#define UART_TX_RST_CORE_V 0x00000001 +#define UART_TX_RST_CORE_S 26 + +/* UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit, reset UART + * Rx. + */ + +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) +#define UART_RX_RST_CORE_V 0x00000001 +#define UART_RX_RST_CORE_S 27 + +/* Status Register */ + +/* UART_STATUS_REG register + * UART status + * register + */ + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) + +/* UART_RXFIFO_CNT : RO; bitpos: [10:0]; default: 0; + * Stores the byte number of valid data in + * Rx-FIFO. + */ + +#define UART_RXFIFO_CNT 0x000003FF +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000003FF +#define UART_RXFIFO_CNT_S 0 + +/* UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr + * signal. + */ + +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001 +#define UART_DSRN_S 13 + +/* UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts + * signal. + */ + +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001 +#define UART_CTSN_S 14 + +/* UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd + * signal. + */ + +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001 +#define UART_RXD_S 15 + +/* UART_TXFIFO_CNT : RO; bitpos: [26:16]; default: 0; + * Stores the byte number of data in + * Tx-FIFO. + */ + +#define UART_TXFIFO_CNT 0x000003FF +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000003FF +#define UART_TXFIFO_CNT_S 16 + +/* UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr + * signal. + */ + +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001 +#define UART_DTRN_S 29 + +/* UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts + * signal. + */ + +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001 +#define UART_RTSN_S 30 + +/* UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd + * signal. + */ + +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001 +#define UART_TXD_S 31 + +/* UART_MEM_TX_STATUS_REG register + * Tx-FIFO write and read offset + * address. + */ + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) + +/* UART_APB_TX_WADDR : RO; bitpos: [10:0]; default: 0; + * This register stores the offset address in Tx-FIFO when software writes + * Tx-FIFO via + * APB. + */ + +#define UART_APB_TX_WADDR 0x000003FF +#define UART_APB_TX_WADDR_M (UART_APB_TX_WADDR_V << UART_APB_TX_WADDR_S) +#define UART_APB_TX_WADDR_V 0x000003FF +#define UART_APB_TX_WADDR_S 0 + +/* UART_TX_RADDR : RO; bitpos: [21:11]; default: 0; + * This register stores the offset address in Tx-FIFO when Tx-FSM reads + * data via + * Tx-FIFO_Ctrl. + */ + +#define UART_TX_RADDR 0x000003FF +#define UART_TX_RADDR_M (UART_TX_RADDR_V << UART_TX_RADDR_S) +#define UART_TX_RADDR_V 0x000003FF +#define UART_TX_RADDR_S 11 + +/* UART_MEM_RX_STATUS_REG register + * Rx-FIFO write and read offset + * address. + */ + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) + +/* UART_APB_RX_RADDR : RO; bitpos: [10:0]; default: 256; + * This register stores the offset address in RX-FIFO when software reads + * data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is + * 10'h180. + */ + +#define UART_APB_RX_RADDR 0x000003FF +#define UART_APB_RX_RADDR_M (UART_APB_RX_RADDR_V << UART_APB_RX_RADDR_S) +#define UART_APB_RX_RADDR_V 0x000003FF +#define UART_APB_RX_RADDR_S 0 + +/* UART_RX_WADDR : RO; bitpos: [21:11]; default: 256; + * This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl + * writes Rx-FIFO. UART0 is 10'h100. UART1 is + * 10'h180. + */ + +#define UART_RX_WADDR 0x000003FF +#define UART_RX_WADDR_M (UART_RX_WADDR_V << UART_RX_WADDR_S) +#define UART_RX_WADDR_V 0x000003FF +#define UART_RX_WADDR_S 11 + +/* UART_FSM_STATUS_REG register + * UART transmit and receive + * status. + */ + +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) + +/* UART_ST_URX_OUT : RO; bitpos: [4:0]; default: 0; + * This is the status register of + * receiver. + */ + +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000F +#define UART_ST_URX_OUT_S 0 + +/* UART_ST_UTX_OUT : RO; bitpos: [8:4]; default: 0; + * This is the status register of + * transmitter. + */ + +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000F +#define UART_ST_UTX_OUT_S 4 + +/* Autobaud Register */ + +/* UART_LOWPULSE_REG register + * Autobaud minimum low pulse duration + * register + */ + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) + +/* UART_LOWPULSE_MIN_CNT : RO; bitpos: [12:0]; default: 4095; + * This register stores the value of the minimum duration time of the low + * level pulse. It is used in baud rate-detect + * process. + */ + +#define UART_LOWPULSE_MIN_CNT 0x00000FFF +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x00000FFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +/* UART_HIGHPULSE_REG register + * Autobaud minimum high pulse duration + * register + */ + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c) + +/* UART_HIGHPULSE_MIN_CNT : RO; bitpos: [12:0]; default: 4095; + * This register stores the value of the maxinum duration time for the + * high level pulse. It is used in baud rate-detect + * process. + */ + +#define UART_HIGHPULSE_MIN_CNT 0x00000FFF +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/* UART_RXD_CNT_REG register + * Autobaud edge change count + * register + */ + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) + +/* UART_RXD_EDGE_CNT : RO; bitpos: [10:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud + * rate-detect + * process. + */ + +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FF +#define UART_RXD_EDGE_CNT_S 0 + +/* UART_POSPULSE_REG register + * Autobaud high pulse + * register + */ + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70) + +/* UART_POSEDGE_MIN_CNT : RO; bitpos: [12:0]; default: 4095; + * This register stores the minimal input clock count between two positive + * edges. It is used in boudrate-detect + * process. + */ + +#define UART_POSEDGE_MIN_CNT 0x00000FFF +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x00000FFF +#define UART_POSEDGE_MIN_CNT_S 0 + +/* UART_NEGPULSE_REG register + * Autobaud low pulse + * register + */ + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74) + +/* UART_NEGEDGE_MIN_CNT : RO; bitpos: [12:0]; default: 4095; + * This register stores the minimal input clock count between two negative + * edges. It is used in boudrate-detect + * process. + */ + +#define UART_NEGEDGE_MIN_CNT 0x00000FFF +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x00000FFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +/* AT Escape Sequence Selection Configuration */ + +/* UART_AT_CMD_PRECNT_REG register + * Pre-sequence timing + * configuration + */ + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50) + +/* UART_PRE_IDLE_NUM : R/W; bitpos: [16:0]; default: 2305; + * This register is used to configure the idle duration time before the + * first at_cmd is received by + * receiver. + */ + +#define UART_PRE_IDLE_NUM 0x0000FFFF +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFF +#define UART_PRE_IDLE_NUM_S 0 + +/* UART_AT_CMD_POSTCNT_REG register + * Post-sequence timing + * configuration + */ + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54) + +/* UART_POST_IDLE_NUM : R/W; bitpos: [16:0]; default: 2305; + * This register is used to configure the duration time between the last + * at_cmd and the next + * data. + */ + +#define UART_POST_IDLE_NUM 0x0000FFFF +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFF +#define UART_POST_IDLE_NUM_S 0 + +/* UART_AT_CMD_GAPTOUT_REG register + * Timeout + * configuration + */ + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58) + +/* UART_RX_GAP_TOUT : R/W; bitpos: [16:0]; default: 11; + * This register is used to configure the duration time between the at_cmd + * chars. + */ + +#define UART_RX_GAP_TOUT 0x0000FFFF +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFF +#define UART_RX_GAP_TOUT_S 0 + +/* UART_AT_CMD_CHAR_REG register + * AT escape sequence detection + * configuration + */ + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c) + +/* UART_AT_CMD_CHAR : R/W; bitpos: [8:0]; default: 43; + * This register is used to configure the content of at_cmd + * char. + */ + +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FF +#define UART_AT_CMD_CHAR_S 0 + +/* UART_CHAR_NUM : R/W; bitpos: [16:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars + * received by + * receiver. + */ + +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FF +#define UART_CHAR_NUM_S 8 + +/* Version Register */ + +/* UART_DATE_REG register + * UART Version + * register + */ + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c) + +/* UART_DATE : R/W; bitpos: [32:0]; default: 33587824; + * This is the version + * register. + */ + +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +/* UART_ID_REG register + * UART ID + * register + */ + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80) + +/* UART_ID : R/W; bitpos: [30:0]; default: 1280; + * This register is used to configure the + * uart_id. + */ + +#define UART_ID 0x3FFFFFFF +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0x3FFFFFFF +#define UART_ID_S 0 + +/* UART_HIGH_SPEED : R/W; bitpos: [30]; default: 1; + * This bit used to select synchronize mode. 1: Registers are auto + * synchronized into UART Core clock and UART core should be keep the same + * with APB clock. 0: After configure registers, software needs to write 1 + * to UART_REG_UPDATE to synchronize + * registers. + */ + +#define UART_HIGH_SPEED (BIT(30)) +#define UART_HIGH_SPEED_M (UART_HIGH_SPEED_V << UART_HIGH_SPEED_S) +#define UART_HIGH_SPEED_V 0x00000001 +#define UART_HIGH_SPEED_S 30 + +/* UART_REG_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * Software write 1 would synchronize registers into UART Core clock + * domain and would be cleared by hardware after synchronization is + * done. + */ + +#define UART_REG_UPDATE (BIT(31)) +#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) +#define UART_REG_UPDATE_V 0x00000001 +#define UART_REG_UPDATE_S 31 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_UART_H */ \ No newline at end of file