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Apply STM32 timer patch from Mike Smith

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4280 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-01-08 00:44:41 +00:00
parent a3864126dc
commit 9a05ff6ae1
1 changed files with 54 additions and 0 deletions
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54
arch/arm/src/stm32/stm32_tim.c
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@ -458,40 +458,76 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
#if CONFIG_STM32_TIM2 #if CONFIG_STM32_TIM2
case STM32_TIM2_BASE: case STM32_TIM2_BASE:
switch(channel) { switch(channel) {
#if defined(GPIO_TIM2_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; case 0: stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break;
#endif
#if defined(GPIO_TIM2_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; case 1: stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break;
#endif
#if defined(GPIO_TIM2_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; case 2: stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break;
#endif
#if defined(GPIO_TIM2_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; case 3: stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break;
#endif
default: return ERROR;
} }
break; break;
#endif #endif
#if CONFIG_STM32_TIM3 #if CONFIG_STM32_TIM3
case STM32_TIM3_BASE: case STM32_TIM3_BASE:
switch(channel) { switch(channel) {
#if defined(GPIO_TIM3_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; case 0: stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break;
#endif
#if defined(GPIO_TIM3_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; case 1: stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break;
#endif
#if defined(GPIO_TIM3_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; case 2: stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break;
#endif
#if defined(GPIO_TIM3_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; case 3: stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break;
#endif
default: return ERROR;
} }
break; break;
#endif #endif
#if CONFIG_STM32_TIM4 #if CONFIG_STM32_TIM4
case STM32_TIM4_BASE: case STM32_TIM4_BASE:
switch(channel) { switch(channel) {
#if defined(GPIO_TIM4_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; case 0: stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break;
#endif
#if defined(GPIO_TIM4_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; case 1: stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break;
#endif
#if defined(GPIO_TIM4_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; case 2: stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break;
#endif
#if defined(GPIO_TIM4_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; case 3: stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break;
#endif
default: return ERROR;
} }
break; break;
#endif #endif
#if CONFIG_STM32_TIM5 #if CONFIG_STM32_TIM5
case STM32_TIM5_BASE: case STM32_TIM5_BASE:
switch(channel) { switch(channel) {
#if defined(GPIO_TIM5_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; case 0: stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break;
#endif
#if defined(GPIO_TIM5_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; case 1: stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break;
#endif
#if defined(GPIO_TIM5_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; case 2: stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break;
#endif
#if defined(GPIO_TIM5_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; case 3: stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break;
#endif
default: return ERROR;
} }
break; break;
#endif #endif
@ -500,20 +536,38 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
#if CONFIG_STM32_TIM1 #if CONFIG_STM32_TIM1
case STM32_TIM1_BASE: case STM32_TIM1_BASE:
switch(channel) { switch(channel) {
#if defined(GPIO_TIM1_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; case 0: stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
#endif
#if defined(GPIO_TIM1_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; case 1: stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
#endif
#if defined(GPIO_TIM1_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; case 2: stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
#endif
#if defined(GPIO_TIM1_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; case 3: stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
#endif
default: return ERROR;
} }
break; break;
#endif #endif
#if CONFIG_STM32_TIM8 #if CONFIG_STM32_TIM8
case STM32_TIM8_BASE: case STM32_TIM8_BASE:
switch(channel) { switch(channel) {
#if defined(GPIO_TIM8_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; case 0: stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
#endif
#if defined(GPIO_TIM8_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; case 1: stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
#endif
#if defined(GPIO_TIM8_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; case 2: stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
#endif
#if defined(GPIO_TIM8_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; case 3: stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
#endif
default: return ERROR;
} }
break; break;
#endif #endif