Add support for DS1302 and DS3232 RTC chips
This commit is contained in:
Gregory Nutt
parent
367d8020be
commit
9a1ca0d489
2
configs
2
configs
@ -1 +1 @@
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Subproject commit 388caf63466f447ce0fc6924dc50e79b9ba70cf8
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Subproject commit 2a5172fbb37ada3f8119c99af34a1bbf70120ee3
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@ -133,7 +133,7 @@ config RTC_EXTERNAL
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early in the boot sequence.
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config RTC_DSXXXX
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bool "DS1307/DS323x RTC Driver"
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bool "DS130x/DS323x RTC Driver"
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default n
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select I2C
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select I2C_TRANSFER
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@ -148,6 +148,11 @@ choice
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prompt "Maxim Integrated RTC"
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default RTC_DS3231
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config RTC_DS1302
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bool "DS1302"
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---help---
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Enables support for the Maxim Integrated DS1307 serial RTC timer.
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config RTC_DS1307
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bool "DS1307"
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---help---
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@ -158,6 +163,11 @@ config RTC_DS3231
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---help---
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Enables support for the Maxim Integrated DS3231 I2C RTC timer.
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config RTC_DS3232
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bool "DS3232"
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---help---
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Enables support for the Maxim Integrated DS3232 I2C RTC timer.
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config RTC_DS3234
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bool "DS3234"
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depends on EXPERIMENTAL
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@ -54,8 +54,8 @@
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# define DSXXXX_TIME_10SEC_MASK (7 << DSXXXX_TIME_10SEC_SHIFT)
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# define DSXXXX_TIME_10SEC(n) ((uint8_t)(n) << DSXXXX_TIME_10SEC_SHIFT)
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# define DSXXXX_TIME_SEC_BCDMASK (DSXXXX_TIME_SEC_MASK | DSXXXX_TIME_10SEC_MASK)
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#ifdef CONFIG_RTC_DS1307
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# define DS1307_TIME_CH (1 << 7) /* Bit 7: Clock halt */
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#if defined(CONFIG_RTC_DS1302) || defined(CONFIG_RTC_DS1307)
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# define DS130x_TIME_CH (1 << 7) /* Bit 7: Clock halt */
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#endif
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#define DSXXXX_TIME_MINR 0x01 /* Minutes register */
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@ -110,7 +110,7 @@
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# define DSXXXX_TIME_10MONTH_MASK (1 << DSXXXX_TIME_10MONTH_SHIFT)
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# define DSXXXX_TIME_10MONTH(n) ((uint8_t)(n) << DSXXXX_TIME_10MONTH_SHIFT)
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# define DSXXXX_TIME_MONTH_BCDMASK (DSXXXX_TIME_MONTH_MASK | DSXXXX_TIME_10MONTH_MASK)
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#if defined(CONFIG_RTC_DS3231) || defined(CONFIG_RTC_DS3234)
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#if defined(CONFIG_RTC_DS3231) || defined(CONFIG_RTC_DS3232) || defined(CONFIG_RTC_DS3234)
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# define DS323X_TIME_CENTURY_SHIFT 7 /* Bit 7: Century Indication */
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# define DS323X_TIME_CENTURY_MASK (1 << DS323X_TIME_CENTURY_SHIFT)
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# define DS323X_TIME_1900 ((uint8_t)(0) << DS323X_TIME_CENTURY_SHIFT)
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@ -126,6 +126,31 @@
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# define DSXXXX_TIME_10YEAR(n) ((uint8_t)(n) << DSXXXX_TIME_10YEAR_SHIFT)
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# define DSXXXX_TIME_YEAR_BCDMASK (DSXXXX_TIME_YEAR_MASK | DSXXXX_TIME_10YEAR_MASK)
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#ifdef CONFIG_RTC_DS1302
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# define DS1302_CR 0x07 /* Control register */
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# define DS1302_CR_WP (1 << 7) /* Bit 7: Write protect */
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# define DS1302_TCR 0x08 /* Trickle charge register */
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# define DS1302_TCR_RS_SHIFT (0) /* Bits 0-1: Range select */
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# define DS1302_TCR_RS_MASK (3 << DS1302_TCR_RS_SHIFT)
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# define DS1302_TCR_RS(n) ((uint8_t)(n) << DS1302_TCR_RS_SHIFT)
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# define DS1302_TCR_DS_SHIFT (4) /* Bits 2-3: Diode select */
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# define DS1302_TCR_DS_MASK (3 << DS1302_TCR_DS_SHIFT)
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# define DS1302_TCR_DS(n) ((uint8_t)(n) << DS1302_TCR_DS_SHIFT)
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# define DS1302_TCR_TCS_SHIFT (4) /* Bits 4-7: Trickle charge select */
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# define DS1302_TCR_TCS_MASK (15 << DS1302_TCR_TCS_SHIFT)
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# define DS1302_TCR_TCS(n) ((uint8_t)(n) << DS1302_TCR_TCS_SHIFT)
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# define DS1302_TCR_DISABLED (DS1302_TCR_RS(0) | define DS1302_TCR_DS(0) | define DS1302_TCR_TCS(0))
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# define DS1302_TCR_1DIODE_2OHM (DS1302_TCR_RS(1) | define DS1302_TCR_DS(1) | define DS1302_TCR_TCS(10))
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# define DS1302_TCR_1DIODE_4OHM (DS1302_TCR_RS(2) | define DS1302_TCR_DS(1) | define DS1302_TCR_TCS(10))
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# define DS1302_TCR_1DIODE_8OHM (DS1302_TCR_RS(3) | define DS1302_TCR_DS(1) | define DS1302_TCR_TCS(10))
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# define DS1302_TCR_2DIODE_2OHM (DS1302_TCR_RS(1) | define DS1302_TCR_DS(2) | define DS1302_TCR_TCS(10))
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# define DS1302_TCR_2DIODE_4OHM (DS1302_TCR_RS(2) | define DS1302_TCR_DS(2) | define DS1302_TCR_TCS(10))
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# define DS1302_TCR_2DIODE_8OHM (DS1302_TCR_RS(3) | define DS1302_TCR_DS(2) | define DS1302_TCR_TCS(10))
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# define DS1302_TCR_INIT (DS1302_TCR_RS(0) | define DS1302_TCR_DS(3) | define DS1302_TCR_TCS(5))
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#endif
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#ifdef CONFIG_RTC_DS1307
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# define DS1307_CR 0x07 /* Control register */
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# define DS1307_CR_RS_SHIFT (3) /* Bits 0-1: Rate selection */
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@ -139,7 +164,7 @@
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# define DS1307_RAM_BASE 0x08 /* 0x08-0x3f: 56x8 RAM */
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#endif
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#if defined(CONFIG_RTC_DS3231) || defined(CONFIG_RTC_DS3234)
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#if defined(CONFIG_RTC_DS3231) || defined(CONFIG_RTC_DS3232) || defined(CONFIG_RTC_DS3234)
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# define DS323X_ALARM1_SECR 0x07 /* Alarm1 seconds register */
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# define DS323X_ALARM1_SEC_SHIFT 0 /* Bits 0-3: Seconds, range 0-9 */
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# define DS323X_ALARM1_SEC_MASK (15 << DS323X_ALARM1_SEC_SHIFT)
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@ -281,14 +306,14 @@
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# define DS323X_CSR_A2F (1 << 1) /* Bit 1: Alarm 2 flag */
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# define DS323X_CSR_BSY (1 << 2) /* Bit 2: Busy */
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# define DS323X_CSR_EN32kHz (1 << 3) /* Bit 3: Enable 32kHz output */
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# ifdef CONFIG_RTC_DS3234
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# define DS3234_CSR_CRATE_SHIFT (4) /* Bits 4-5: Conversion rate */
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# define DS3234_CSR_CRATE_MASK (3 << DS3234_CSR_CRATE_SHIFT)
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# define DS3234_CSR_CRATE_64SEC (0 << DS3234_CSR_CRATE_SHIFT)
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# define DS3234_CSR_CRATE_128SEC (1 << DS3234_CSR_CRATE_SHIFT)
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# define DS3234_CSR_CRATE_256SEC (2 << DS3234_CSR_CRATE_SHIFT)
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# define DS3234_CSR_CRATE_512SEC (3 << DS3234_CSR_CRATE_SHIFT)
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# define DS3234_CSR_BB32KHZ (1 << 6) /* Bit 6: Battery-Backed 32kHz Output */
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# if defined(CONFIG_RTC_DS3232) || defined(CONFIG_RTC_DS3234)
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# define DS323x_CSR_CRATE_SHIFT (4) /* Bits 4-5: Conversion rate */
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# define DS323x_CSR_CRATE_MASK (3 << DS323x_CSR_CRATE_SHIFT)
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# define DS323x_CSR_CRATE_64SEC (0 << DS323x_CSR_CRATE_SHIFT)
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# define DS323x_CSR_CRATE_128SEC (1 << DS323x_CSR_CRATE_SHIFT)
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# define DS323x_CSR_CRATE_256SEC (2 << DS323x_CSR_CRATE_SHIFT)
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# define DS323x_CSR_CRATE_512SEC (3 << DS323x_CSR_CRATE_SHIFT)
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# define DS323x_CSR_BB32KHZ (1 << 6) /* Bit 6: Battery-Backed 32kHz Output */
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# endif
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# define DS323X_CSR_OSF (1 << 7) /* Bit 7: Oscillator stop flag */
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@ -298,7 +323,11 @@
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# define DS323X_TMPLR 0x12 /* LSB of temp register (2-bits) */
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# define DS323X_TMPLR_MASK 0xc0 /* Bits 6-7: LSB of temp register (2-bits) */
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#endif /* CONFIG_RTC_DS3231 || CONFIG_RTC_DS3234 */
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#endif /* CONFIG_RTC_DS3231 || CONFIG_RTC_DS3232 || CONFIG_RTC_DS3234 */
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#ifdef CONFIG_RTC_DS3232
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# define DS3232_SRAM_BASE 0x14 /* 0x14-0xff: SRAM */
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#endif /* CONFIG_RTC_DS3232 */
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#ifdef CONFIG_RTC_DS3234
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# define DS3234_SRAM_ADDRR 0x98 /* SRAM address register */
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