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fix bug in gd32f4xx_serial.c, add romfsimg.h, gd32f4xx_reset and improve gd32f4xx_gpio.c for f470z board, add board decription for f470

Browse Source 
add gd32f470 picture
This commit is contained in:
GD32-MCU 2023-12-12 19:54:17 +08:00 committed by Xiang Xiao
parent 5f631e2b2b
commit 9a2569882e
12 changed files with 358 additions and 23 deletions
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BIN
Documentation/platforms/arm/gd32f4/boards/gd32f470zk-eval/gd32f470z_eval.png Executable file
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11
Documentation/platforms/arm/gd32f4/boards/gd32f470zk-eval/index.rst
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@ -2,3 +2,14 @@
gd32f470zk-eval
===============
The GD32F470Z-EVAL board is a hardware platform that enables prototyping
on GD32F470ZK Cortex-M4F Stretch Performance MCU.
The GD32F470ZK features a single-core ARM Cortex-M4F MCU which can run up
to 240 MHz with flash accesses zero wait states, 3072kiB of Flash, 256kiB
of SRAM and 114 GPIOs.
.. figure:: gd32f470z_eval.png
:align: center
:alt: gd32f470z_eval

53
Documentation/platforms/arm/gd32f4/index.rst
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@ -2,6 +2,59 @@
GD32F4
======
The devices of GD32F4xx series are 32-bit general-purpose microcontrollers
based on the Cortex-M4 processor. The Cortex-M4 processor includes three
AHB buses known as I-Code, D-Code and System buses. All memory accesses of
the Cortex-M4 processor are executed on the three buses according to the
different purposes and the target memory spaces. The memory organization
uses a Harvard architecture, pre-defined memory map and up to 4 GB of
memory space, making the system flexible and extendable.
Supported MCUs
==============
TODO
Peripheral Support
==================
The following list indicates peripherals now supported
in NuttX:
========== ======= =====
Peripheral Support Notes
========== ======= =====
SYSCFG Yes
FMC Yes
PMU yes
RCU Yes
GPIO Yes
DMA Yes
IPA no
EXTI Yes
SPI Yes
TLI no
I2C Yes
USART Yes
I2S no
SDIO yes
ENET Yes
========== ======= =====
Memory
------
- CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)
- CONFIG_RAM_START - The start address of installed DRAM
- CONFIG_GD32_TCMEXCLUDE - Exclude TCM SRAM from the HEAP
- CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
stack. If defined, this symbol is the size of the interrupt
stack in bytes. If not defined, the user task stacks will be
used during interrupt handling.
Supported Boards
================

14
arch/arm/src/gd32f4/gd32f4xx_serial.c
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@ -118,7 +118,7 @@ struct up_dev_s
bool oflow; /* output flow control (CTS) enabled */
# endif
uint16_t oversamp /* USART oversample mode */
uint16_t oversamp; /* USART oversample mode */
uintptr_t usartbase; /* Base address of UART registers */
uint32_t baud; /* Configured baud */
uint32_t clock; /* Frequency of the UART */
@ -1214,14 +1214,6 @@ static void gd32_usart_configure(struct uart_dev_s *dev)
uint32_t fradiv;
uint32_t regval;
/* Reset USART */
gd32_usart_reset(priv->usartbase);
/* Enable USART clock */
gd32_usart_clock_enable(priv->usartbase);
/* Configure the USART oversample mode. */
regval = up_serialin(priv, GD32_USART_CTL0_OFFSET);
@ -1335,6 +1327,10 @@ static int up_setup(struct uart_dev_s *dev)
#ifndef CONFIG_SUPPRESS_UART_CONFIG
uint32_t regval;
/* Enable USART clock */
gd32_usart_clock_enable(priv->usartbase);
/* Configure pins for USART use */
gd32_gpio_config(priv->tx_gpio);

2
boards/arm/gd32f4/gd32f470zk-eval/include/board.h
View File

@ -134,7 +134,7 @@
*/
#define GD32_PLL_PLLPSC RCU_PLL_PLLPSC(25)
#define GD32_PLL_PLLN RCU_PLL_PLLN(336)
#define GD32_PLL_PLLN RCU_PLL_PLLN(480)
#define GD32_PLL_PLLP RCU_PLL_PLLP(2)
#define GD32_PLL_PLLQ RCU_PLL_PLLQ(7)

111
boards/arm/gd32f4/gd32f470zk-eval/include/nsh_romfsimg.h Normal file
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@ -0,0 +1,111 @@
/***************************************************************************
* boards/arm/gd32f4/gd32f470zk-eval/include/nsh_romfsimg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
***************************************************************************/
const unsigned char romfs_img[] =
{
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
};
const unsigned int romfs_img_len = 1024;

3
boards/arm/gd32f4/gd32f470zk-eval/scripts/kernel-space.ld
View File

@ -45,7 +45,8 @@ SECTIONS
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP(*(.init_array .ctors))
_einit = ABSOLUTE(.);
} > kflash

3
boards/arm/gd32f4/gd32f470zk-eval/scripts/ld.script
View File

@ -61,7 +61,8 @@ SECTIONS
.init_section : ALIGN(4) {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP(*(.init_array .ctors))
_einit = ABSOLUTE(.);
} > flash

3
boards/arm/gd32f4/gd32f470zk-eval/scripts/user-space.ld
View File

@ -59,7 +59,8 @@ SECTIONS
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP(*(.init_array .ctors))
_einit = ABSOLUTE(.);
} > uflash

4
boards/arm/gd32f4/gd32f470zk-eval/src/Makefile
View File

@ -61,4 +61,8 @@ ifeq ($(CONFIG_MTD_AT24XX), y)
CSRCS += gd32f4xx_at24.c
endif
ifeq ($(CONFIG_BOARDCTL_RESET), y)
CSRCS += gd32f4xx_reset.c
endif
include $(TOPDIR)/boards/Board.mk

115
boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_gpio.c
View File

@ -48,6 +48,7 @@
struct gd32gpio_dev_s
{
struct gpio_dev_s gpio;
uint32_t pinconfig;
uint8_t id;
};
@ -163,12 +164,102 @@ static struct gd32gpint_dev_s g_gpint[BOARD_NGPIOINT];
static int gpio_setpintype(struct gpio_dev_s *dev,
enum gpio_pintype_e gpio_pintype)
{
int ret = OK;
uint32_t pinconfig;
const struct gpio_operations_s *gpio_ops;
struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)dev;
UNUSED(gd32gpint);
UNUSED(gpio_pintype);
DEBUGASSERT(gd32gpint != NULL);
gpioinfo("Setpintype...\n");
gpioinfo("setpintype is not supported. \n");
/* Check if the new pintype is actually different from the old pintype */
if (gd32gpint->gd32gpio.gpio.gp_pintype == gpio_pintype)
{
/* Pintype has not changed. We're done already. */
return ret;
}
if (gd32gpint->gd32gpio.gpio.gp_pintype >= GPIO_NPINTYPES)
{
gpioerr("pintype error\n");
return -1;
}
pinconfig = (gd32gpint->gd32gpio.pinconfig &
(GPIO_CFG_PIN_MASK | GPIO_CFG_PORT_MASK));
switch (gpio_pintype)
{
case GPIO_INPUT_PIN:
gd32_gpio_config(GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_NONE |
pinconfig);
gpio_ops = &gpin_ops;
break;
case GPIO_INPUT_PIN_PULLUP:
gd32_gpio_config(GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_PULLUP |
pinconfig);
gpio_ops = &gpin_ops;
break;
case GPIO_INPUT_PIN_PULLDOWN:
gd32_gpio_config(GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_PULLDOWN |
pinconfig);
gpio_ops = &gpin_ops;
break;
case GPIO_OUTPUT_PIN:
gd32_gpio_config(GPIO_CFG_MODE_OUTPUT | GPIO_CFG_PP |
GPIO_CFG_SPEED_50MHZ | pinconfig);
gpio_ops = &gpout_ops;
break;
case GPIO_OUTPUT_PIN_OPENDRAIN:
gd32_gpio_config(GPIO_CFG_MODE_OUTPUT | GPIO_CFG_OD |
GPIO_CFG_SPEED_50MHZ | pinconfig);
gpio_ops = &gpout_ops;
break;
case GPIO_INTERRUPT_PIN:
case GPIO_INTERRUPT_RISING_PIN:
case GPIO_INTERRUPT_FALLING_PIN:
case GPIO_INTERRUPT_BOTH_PIN:
gd32_gpio_config(GPIO_CFG_MODE_INPUT | GPIO_PUPD_NONE |
pinconfig);
gpio_ops = &gpint_ops;
break;
default:
/* Not support! */
return -EINVAL;
break;
}
/* If the pin previously had an interrupt pintype... */
if ((gd32gpint->gd32gpio.gpio.gp_pintype >= GPIO_INTERRUPT_PIN) &&
(gd32gpint->gd32gpio.gpio.gp_pintype < GPIO_NPINTYPES))
{
/* ...disable the interrupt... */
ret = gpint_enable(dev, false);
if (ret < 0)
{
return ret;
}
/* ...and detach the old callback. */
ret = gpint_attach(dev, NULL);
if (ret < 0)
{
return ret;
}
}
/* Change the pintype and set of operations */
gd32gpint->gd32gpio.gpio.gp_pintype = gpio_pintype;
gd32gpint->gd32gpio.gpio.gp_ops = gpio_ops;
gd32gpint->gd32gpio.pinconfig = pinconfig;
return 0;
}
@ -179,10 +270,10 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value)
struct gd32gpio_dev_s *gd32gpio = (struct gd32gpio_dev_s *)dev;
DEBUGASSERT(gd32gpio != NULL && value != NULL);
DEBUGASSERT(gd32gpio->id < BOARD_NGPIOIN);
gpioinfo("Reading...\n");
*value = gd32_gpio_read(g_gpioinputs[gd32gpio->id]);
*value = gd32_gpio_read(gd32gpio->pinconfig);
return OK;
}
#endif
@ -193,10 +284,10 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value)
struct gd32gpio_dev_s *gd32gpio = (struct gd32gpio_dev_s *)dev;
DEBUGASSERT(gd32gpio != NULL && value != NULL);
DEBUGASSERT(gd32gpio->id < BOARD_NGPIOOUT);
gpioinfo("Reading...\n");
*value = gd32_gpio_read(g_gpiooutputs[gd32gpio->id]);
*value = gd32_gpio_read(gd32gpio->pinconfig);
return OK;
}
@ -205,10 +296,10 @@ static int gpout_write(struct gpio_dev_s *dev, bool value)
struct gd32gpio_dev_s *gd32gpio = (struct gd32gpio_dev_s *)dev;
DEBUGASSERT(gd32gpio != NULL);
DEBUGASSERT(gd32gpio->id < BOARD_NGPIOOUT);
gpioinfo("Writing %d\n", (int)value);
gd32_gpio_write(g_gpiooutputs[gd32gpio->id], value);
gd32_gpio_write(gd32gpio->pinconfig, value);
return OK;
}
#endif
@ -234,7 +325,8 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value)
DEBUGASSERT(gd32gpint->gd32gpio.id < BOARD_NGPIOINT);
gpioinfo("Reading int pin...\n");
*value = gd32_gpio_read(g_gpiointinputs[gd32gpint->gd32gpio.id]);
*value = gd32_gpio_read(gd32gpint->gd32gpio.pinconfig);
return OK;
}
@ -342,6 +434,7 @@ int gd32_gpio_initialize(void)
g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN;
g_gpin[i].gpio.gp_ops = &gpin_ops;
g_gpin[i].pinconfig = g_gpioinputs[i];
g_gpin[i].id = i;
gpio_pin_register(&g_gpin[i].gpio, pincount);
@ -361,6 +454,7 @@ int gd32_gpio_initialize(void)
g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN;
g_gpout[i].gpio.gp_ops = &gpout_ops;
g_gpout[i].pinconfig = g_gpiooutputs[i];
g_gpout[i].id = i;
gpio_pin_register(&g_gpout[i].gpio, pincount);
@ -381,6 +475,7 @@ int gd32_gpio_initialize(void)
g_gpint[i].gd32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN;
g_gpint[i].gd32gpio.gpio.gp_ops = &gpint_ops;
g_gpint[i].gd32gpio.pinconfig = g_gpiointinputs[i];
g_gpint[i].gd32gpio.id = i;
(void)gpio_pin_register(&g_gpint[i].gd32gpio.gpio, pincount);

62
boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_reset.c Normal file
View File

@ -0,0 +1,62 @@
/****************************************************************************
* boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_reset.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#ifdef CONFIG_BOARDCTL_RESET
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_reset
*
* Description:
* Reset board. Support for this function is required by board-level
* logic if CONFIG_BOARDCTL_RESET is selected.
*
* Input Parameters:
* status - Status information provided with the reset event. This
* meaning of this status information is board-specific. If not
* used by a board, the value zero may be provided in calls to
* board_reset().
*
* Returned Value:
* If this function returns, then it was not possible to power-off the
* board due to some constraints. The return value int this case is a
* board-specific reason for the failure to shutdown.
*
****************************************************************************/
int board_reset(int status)
{
up_systemreset();
return 0;
}
#endif /* CONFIG_BOARDCTL_RESET */