arch/arm/src/tiva/hardware: Add CC13x0 AUX WUC register definition header file.
This commit is contained in:
Gregory Nutt
parent
64921a9c57
commit
9a25e86416
@ -50,6 +50,7 @@
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#include "hardware/tiva_aon_ioc.h"
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#include "hardware/tiva_aon_sysctl.h"
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#include "hardware/tiva_aon_wuc.h"
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#include "hardware/tiva_aux_wuc.h"
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#include "hardware/tiva_ccfg.h"
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#include "hardware/tiva_fcfg1.h"
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#include "hardware/tiva_flash.h"
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@ -300,7 +301,7 @@ void cc13xx_trim_device(void)
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* workaround)
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*/
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putreg32(AUX_WUC_MODCLKEN1_SMPH, TIVA_AON_WUC_MODCLKEN1);
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putreg32(AUX_WUC_MODCLKEN1_SMPH, TIVA_AUX_WUC_MODCLKEN1);
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/* Warm resets on CC13x0 and CC26x0 complicates software design because much
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* of our software expect that initialization is done from a full system
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@ -311,7 +312,7 @@ void cc13xx_trim_device(void)
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regval = getreg32(TIVA_PRCM_WARMRESET);
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regval |= PRCM_WARMRESET_WRTO_PINRESET;
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putreg32(regval, TIVA_PRCM_WARMRESET)
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putreg32(regval, TIVA_PRCM_WARMRESET);
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/* Select correct CACHE mode and set correct CACHE configuration */
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206
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h
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206
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h
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@ -0,0 +1,206 @@
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/********************************************************************************************************************
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* arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_WUC_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_WUC_H
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/********************************************************************************************************************
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* Included Files
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********************************************************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/tiva_memorymap.h"
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/********************************************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************************************/
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/* AUX WUC Register Offsets *****************************************************************************************/
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#define TIVA_AUX_WUC_MODCLKEN0_OFFSET 0x0000 /* Module Clock Enable */
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#define TIVA_AUX_WUC_PWROFFREQ_OFFSET 0x0004 /* Power Off Request */
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#define TIVA_AUX_WUC_PWRDWNREQ_OFFSET 0x0008 /* Power Down Request */
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#define TIVA_AUX_WUC_PWRDWNACK_OFFSET 0x000c /* Power Down Acknowledgment */
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#define TIVA_AUX_WUC_CLKLFREQ_OFFSET 0x0010 /* Low Frequency Clock Request */
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#define TIVA_AUX_WUC_CLKLFACK_OFFSET 0x0014 /* Low Frequency Clock Acknowledgment */
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#define TIVA_AUX_WUC_WUEVFLAGS_OFFSET 0x0028 /* Wake-up Event Flags */
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#define TIVA_AUX_WUC_WUEVCLR_OFFSET 0x002c /* Wake-up Event Clear */
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#define TIVA_AUX_WUC_ADCCLKCTL_OFFSET 0x0030 /* ADC Clock Control */
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#define TIVA_AUX_WUC_TDCCLKCTL_OFFSET 0x0034 /* ADC Clock Control */
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#define TIVA_AUX_WUC_REFCLKCTL_OFFSET 0x0038 /* ADC Clock Control */
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#define TIVA_AUX_WUC_RTCSUBSECINC0_OFFSET 0x003c /* Real Time Counter Sub Second Increment 0 */
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#define TIVA_AUX_WUC_RTCSUBSECINC1_OFFSET 0x0040 /* Real Time Counter Sub Second Increment 1 */
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#define TIVA_AUX_WUC_RTCSUBSECINCCTL_OFFSET 0x0044 /* Real Time Counter Sub Second Increment Control */
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#define TIVA_AUX_WUC_MCUBUSCTL_OFFSET 0x0048 /* MCU Bus Control */
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#define TIVA_AUX_WUC_MCUBUSSTAT_OFFSET 0x004c /* MCU Bus Status */
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#define TIVA_AUX_WUC_AONCTLSTAT_OFFSET 0x0050 /* AON Domain Control Status */
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#define TIVA_AUX_WUC_AUXIOLATCH_OFFSET 0x0054 /* AUX Input Output Latch */
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#define TIVA_AUX_WUC_MODCLKEN1_OFFSET 0x005c /* Module Clock Enable 1 */
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/* AUX WUC Register Addresses ***************************************************************************************/
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#define TIVA_AUX_WUC_MODCLKEN0 (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_MODCLKEN0_OFFSET)
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#define TIVA_AUX_WUC_PWROFFREQ (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_PWROFFREQ_OFFSET)
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#define TIVA_AUX_WUC_PWRDWNREQ (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_PWRDWNREQ_OFFSET)
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#define TIVA_AUX_WUC_PWRDWNACK (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_PWRDWNACK_OFFSET)
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#define TIVA_AUX_WUC_CLKLFREQ (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_CLKLFREQ_OFFSET)
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#define TIVA_AUX_WUC_CLKLFACK (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_CLKLFACK_OFFSET)
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#define TIVA_AUX_WUC_WUEVFLAGS (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_WUEVFLAGS_OFFSET)
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#define TIVA_AUX_WUC_WUEVCLR (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_WUEVCLR_OFFSET)
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#define TIVA_AUX_WUC_ADCCLKCTL (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_ADCCLKCTL_OFFSET)
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#define TIVA_AUX_WUC_TDCCLKCTL (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_TDCCLKCTL_OFFSET)
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#define TIVA_AUX_WUC_REFCLKCTL (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_REFCLKCTL_OFFSET)
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#define TIVA_AUX_WUC_RTCSUBSECINC0 (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_RTCSUBSECINC0_OFFSET)
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#define TIVA_AUX_WUC_RTCSUBSECINC1 (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_RTCSUBSECINC1_OFFSET)
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#define TIVA_AUX_WUC_RTCSUBSECINCCTL (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_RTCSUBSECINCCTL_OFFSET)
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#define TIVA_AUX_WUC_MCUBUSCTL (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_MCUBUSCTL_OFFSET)
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#define TIVA_AUX_WUC_MCUBUSSTAT (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_MCUBUSSTAT_OFFSET)
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#define TIVA_AUX_WUC_AONCTLSTAT (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_AONCTLSTAT_OFFSET)
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#define TIVA_AUX_WUC_AUXIOLATCH (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_AUXIOLATCH_OFFSET)
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#define TIVA_AUX_WUC_MODCLKEN1 (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_MODCLKEN1_OFFSET)
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/* AUX WUC Register Bitfield Definitions ****************************************************************************/
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/* AUX_WUC_MODCLKEN0 */
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#define AUX_WUC_MODCLKEN0_SMPH (1 << 0) /* Bit 0: Enable clock for AUX_SMPH */
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#define AUX_WUC_MODCLKEN0_AIODIO0 (1 << 1) /* Bit 1: Enable clock for AUX_AIODIO0 */
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#define AUX_WUC_MODCLKEN0_AIODIO1 (1 << 2) /* Bit 2: Enable clock for AUX_AIODIO1 */
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#define AUX_WUC_MODCLKEN0_TIMER (1 << 3) /* Bit 3: Enable clock for AUX_TIMER */
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#define AUX_WUC_MODCLKEN0_ANAIF (1 << 4) /* Bit 4: Enable clock for AUX_ANAIF */
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#define AUX_WUC_MODCLKEN0_TDC (1 << 5) /* Bit 5: Enable clock for AUX_TDCIF */
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#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC (1 << 6) /* Bit 6: Enable clock for AUX_DDI0_OSC */
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#define AUX_WUC_MODCLKEN0_AUX_ADI4 (1 << 7) /* Bit 7: Enable clock for AUX_ADI4 */
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/* AUX_WUC_PWROFFREQ */
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#define AUX_WUC_PWROFFREQ_REQ (1 << 0) /* Bit 0: Power off request */
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/* AUX_WUC_PWRDWNREQ */
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#define AUX_WUC_PWRDWNREQ_REQ (1 << 0) /* Bit 0: Power down request */
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/* AUX_WUC_PWRDWNACK */
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#define AUX_WUC_PWRDWNACK_ACK (1 << 0) /* Bit 0: Power down acknowledgment */
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/* AUX_WUC_CLKLFREQ */
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#define AUX_WUC_CLKLFREQ_REQ (1 << 0) /* Bit 0: Low frequency request */
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/* AUX_WUC_CLKLFACK */
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#define AUX_WUC_CLKLFACK_ACK (1 << 0) /* Bit 0: Acknowledge low free frequency clock */
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/* AUX_WUC_WUEVFLAGS */
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#define AUX_WUC_WUEVFLAGS_AON_PROG_WU (1 << 0) /* Bit 0: Pending event trigged by sources select in
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* AON_EVENT:AUXWUSEL.WU0_EV, WU1_EV, and WU2_EV */
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#define AUX_WUC_WUEVFLAGS_AON_SW (1 << 1) /* Bit 1: Pending event triggered by write to
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* ON_WUC:AUXCTL.SWEV */
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#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 (1 << 2) /* Bit 2: Pending event from AON_RTC_CH2 compare */
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/* AUX_WUC_WUEVCLR */
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#define AUX_WUC_WUEVCLR_AON_PROG_WU (1 << 0) /* Bit 0: Clear WUEVFLAGS.AON_PROG_WU wake-up event */
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#define AUX_WUC_WUEVCLR_AON_SW (1 << 1) /* Bit 1: Clear WUEVFLAGS.AON_SW wake-up event */
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#define AUX_WUC_WUEVCLR_AON_RTC_CH2 (1 << 2) /* Bit 2: Clear WUEVFLAGS.AON_RTC_CH2 wake-up event */
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/* AUX_WUC_ADCCLKCTL */
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#define AUX_WUC_ADCCLKCTL_REQ (1 << 0) /* Bit 0: Enable ADC internal clock */
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#define AUX_WUC_ADCCLKCTL_ACK (1 << 1) /* Bit 1: Acknowledge last value written to REQ */
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/* AUX_WUC_TDCCLKCTL */
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#define AUX_WUC_TDCCLKCTL_REQ (1 << 0) /* Bit 0: Enable TDC counter clock source */
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#define AUX_WUC_TDCCLKCTL_ACK (1 << 1) /* Bit 1: Acknowledge last value written to REQ */
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/* AUX_WUC_REFCLKCTL */
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#define AUX_WUC_REFCLKCTL_REQ (1 << 0) /* Bit 0: Enable TDC reference clock source */
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#define AUX_WUC_REFCLKCTL_ACK (1 << 1) /* Bit 1: Acknowledge last value written to REQ */
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/* AUX_WUC_RTCSUBSECINC0 */
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#define AUX_WUC_RTCSUBSECINC0_INC15_0_SHIFT (0) /* Bits 0-15: Bits 0-15 of RTC sub-second increment */
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#define AUX_WUC_RTCSUBSECINC0_INC15_0_MASK (0xffff << AUX_WUC_RTCSUBSECINC0_INC15_0_SHIFT)
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# define AUX_WUC_RTCSUBSECINC0_INC15_0(n) ((uint32_t)(n) << AUX_WUC_RTCSUBSECINC0_INC15_0_SHIFT)
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/* AUX_WUC_RTCSUBSECINC1 */
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#define AUX_WUC_RTCSUBSECINC1_INC23_16_SHIFT (0) /* Bits 0-7: Bits 15-23 of RTC sub-second increment */
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#define AUX_WUC_RTCSUBSECINC1_INC23_16_MASK (0xff << AUX_WUC_RTCSUBSECINC1_INC23_16_SHIFT)
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# define AUX_WUC_RTCSUBSECINC1_INC23_16(n) ((uint32_t)(n) << AUX_WUC_RTCSUBSECINC1_INC23_16_SHIFT)
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/* AUX_WUC_RTCSUBSECINCCTL */
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#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ (1 << 0) /* Bit 0: New RTC sub-second increment available */
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#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK (1 << 1) /* Bit 1: Acknowledgment of UPD_REQ */
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/* AUX_WUC_MCUBUSCTL */
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#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ (1 << 0) /* Bit 0: Request AUX domain disconnect from MCU domain */
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/* AUX_WUC_MCUBUSSTAT */
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#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK (1 << 0) /* Bit 0: Acknowledge bus disconnection request */
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#define AUX_WUC_MCUBUSSTAT_DISCONNECTED (1 << 1) /* Bit 1: AUX and MCU domain buses disconnected */
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/* AUX_WUC_AONCTLSTAT */
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#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN (1 << 0) /* Bit 0: Status of AON_WUC:AUX_CTL.SCE_RUN_EN */
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#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON (1 << 1) /* Bit 1: Status of AON_WUC:AUX_CTL.AUX_FORCE_ON */
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/* AUX_WUC_AUXIOLATCH */
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#define AUX_WUC_AUXIOLATCH_EN (1 << 0) /* Bit 0: Open AUX_AIODIO0/AUX_AIODIO1 signal latching */
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/* AUX_WUC_MODCLKEN1 */
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#define AUX_WUC_MODCLKEN1_SMPH (1 << 0) /* Bit 0: Enable clock for AUX_SMPH */
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#define AUX_WUC_MODCLKEN1_AIODIO0 (1 << 1) /* Bit 1: Enable clock for AUX_AIODIO0 */
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#define AUX_WUC_MODCLKEN1_AIODIO1 (1 << 2) /* Bit 2: Enable clock for AUX_AIODIO1 */
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#define AUX_WUC_MODCLKEN1_TIMER (1 << 3) /* Bit 3: Enable clock for AUX_TIMER */
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#define AUX_WUC_MODCLKEN1_ANAIF (1 << 4) /* Bit 4: Enable clock for AUX_ANAIF */
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#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC (1 << 6) /* Bit 6: Enable clock for AUX_DDI0_OSC */
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#define AUX_WUC_MODCLKEN1_AUX_ADI4 (1 << 7) /* Bit 7: Enable clock for AUX_ADI4 */
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#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_WUC_H */
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72
arch/arm/src/tiva/hardware/tiva_aux_wuc.h
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72
arch/arm/src/tiva/hardware/tiva_aux_wuc.h
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@ -0,0 +1,72 @@
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/************************************************************************************
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* arch/arm/src/tiva/hardware/tiva_aux_wuc.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_WUC_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_WUC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */
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#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) || \
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defined(CONFIG_ARCH_CHIP_CC13X2)
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/* These architectures do not support the AUX WUC block */
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#elif defined(CONFIG_ARCH_CHIP_CC13X0)
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# include "hardware/cc13x0/cc13x0_aux_wuc.h"
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#else
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# error "Unsupported Tiva/Stellaris/SimpleLink AUX WUC"
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_WUC_H */
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