stm32: stm32_flash: add EEPROM writing for STM32L15XX
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@ -59,16 +59,33 @@
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#if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT)
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# if defined(CONFIG_STM32_STM32L15XX)
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# if defined(CONFIG_STM32_HIGHDENSITY)
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/* The STM32 L15xx/L16xx can support up to 384KB of FLASH. (In reality, supported
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* L15xx parts have no more than 128KB). The program memory block is divided into
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* 96 sectors of 4 Kbytes each, and each sector is further split up into 16 pages of
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* 256 bytes each. The sector is the write protection granularity. In total, the
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/* Different STM32L1xxx MCU version are now called by different 'categories' instead
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* of 'densities'. Cat.5 MCU can have up to 512KB of FLASH. STM32L1xxx also have
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* data EEPROM, up to 16KB.
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*/
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# define STM32_FLASH_NPAGES 2048
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# define STM32_FLASH_PAGESIZE 256
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# else
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/* The STM32 (< Cat.5) L15xx/L16xx can support up to 384KB of FLASH. (In reality, most
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* supported L15xx parts have no more than 128KB). The program memory block is divided
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* into 96 sectors of 4 Kbytes each, and each sector is further split up into 16 pages
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* of 256 bytes each. The sector is the write protection granularity. In total, the
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* program memory block contains 1536 pages.
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*/
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# define STM32_FLASH_NPAGES 1536
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# define STM32_FLASH_PAGESIZE 256
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# define STM32_FLASH_NPAGES 1536
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# define STM32_FLASH_PAGESIZE 256
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# endif
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/* Maximum EEPROM size on Cat.5 MCU. TODO: this should be in chip config. */
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# ifndef STM32_EEPROM_SIZE
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# define STM32_EEPROM_SIZE (16 * 1024)
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# endif
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# elif defined(CONFIG_STM32_LOWDENSITY)
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# define STM32_FLASH_NPAGES 32
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@ -201,27 +218,40 @@
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# elif defined(CONFIG_STM32_FLASH_CONFIG_I)
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# endif
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# endif
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#endif
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#endif /* !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) */
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#ifdef STM32_FLASH_PAGESIZE
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# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
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#endif /* def STM32_FLASH_PAGESIZE */
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#endif
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/* Register Offsets *****************************************************************/
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#define STM32_FLASH_ACR_OFFSET 0x0000
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#define STM32_FLASH_KEYR_OFFSET 0x0004
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#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
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#define STM32_FLASH_SR_OFFSET 0x000c
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#define STM32_FLASH_CR_OFFSET 0x0010
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
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defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
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# define STM32_FLASH_AR_OFFSET 0x0014
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# define STM32_FLASH_OBR_OFFSET 0x001c
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# define STM32_FLASH_WRPR_OFFSET 0x0020
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#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define STM32_FLASH_OPTCR_OFFSET 0x0014
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#define STM32_FLASH_ACR_OFFSET 0x0000
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#if defined(CONFIG_STM32_STM32L15XX)
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# define STM32_FLASH_PECR_OFFSET 0x0004
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# define STM32_FLASH_PDKEYR_OFFSET 0x0008
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# define STM32_FLASH_PEKEYR_OFFSET 0x000c
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# define STM32_FLASH_PRGKEYR_OFFSET 0x0010
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# define STM32_FLASH_OPTKEYR_OFFSET 0x0014
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# define STM32_FLASH_SR_OFFSET 0x0018
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# define STM32_FLASH_OBR_OFFSET 0x001c
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# define STM32_FLASH_WRPR1_OFFSET 0x0020
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# define STM32_FLASH_WRPR2_OFFSET 0x0080
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# define STM32_FLASH_WRPR3_OFFSET 0x0084
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# define STM32_FLASH_WRPR4_OFFSET 0x0088
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#else
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# define STM32_FLASH_KEYR_OFFSET 0x0004
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# define STM32_FLASH_OPTKEYR_OFFSET 0x0008
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# define STM32_FLASH_SR_OFFSET 0x000c
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# define STM32_FLASH_CR_OFFSET 0x0010
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# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
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defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
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# define STM32_FLASH_AR_OFFSET 0x0014
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# define STM32_FLASH_OBR_OFFSET 0x001c
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# define STM32_FLASH_WRPR_OFFSET 0x0020
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# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define STM32_FLASH_OPTCR_OFFSET 0x0014
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# endif
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#endif
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#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
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@ -230,22 +260,36 @@
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/* Register Addresses ***************************************************************/
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#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
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#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
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#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
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#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
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#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
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#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
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#if defined(CONFIG_STM32_STM32L15XX)
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# define STM32_FLASH_PECR (STM32_FLASHIF_BASE+STM32_FLASH_PECR_OFFSET)
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# define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET)
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# define STM32_FLASH_PEKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PEKEYR_OFFSET)
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# define STM32_FLASH_PRGKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PRGKEYR_OFFSET)
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# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
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# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
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# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
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# define STM32_FLASH_WRPR1 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR1_OFFSET)
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# define STM32_FLASH_WRPR2 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR2_OFFSET)
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# define STM32_FLASH_WRPR3 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR3_OFFSET)
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# define STM32_FLASH_WRPR4 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR4_OFFSET)
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#else
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# define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
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# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
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# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
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# define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
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defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
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# define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
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# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
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# define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
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#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
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#endif
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#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
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# define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET)
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# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
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defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
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# define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
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# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
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# define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
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# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
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# endif
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# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
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# define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET)
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# endif
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#endif
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/* Register Bitfield Definitions ****************************************************/
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@ -303,6 +347,34 @@
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# define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */
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# define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
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# define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
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#elif defined(CONFIG_STM32_STM32L15XX)
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# define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */
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# define FLASH_SR_EOP (1 << 1) /* Bit 1: End of operation */
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# define FLASH_SR_ENDHV (1 << 2) /* Bit 2: End of high voltage */
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# define FLASH_SR_READY (1 << 3) /* Bit 3: Flash memory module ready after low power mode */
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# define FLASH_SR_WRPERR (1 << 8) /* Bit 8: Write protection error */
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# define FLASH_SR_PGAERR (1 << 9) /* Bit 9: Programming alignment error */
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# define FLASH_SR_SIZERR (1 << 10) /* Bit 10: Size error */
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# define FLASH_SR_OPTVERR (1 << 11) /* Bit 11: Option validity error */
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# define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */
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# define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */
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#endif
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/* Program/Erase Control Register (PECR) */
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#if defined(CONFIG_STM32_STM32L15XX)
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# define FLASH_PECR_PELOCK (1 << 0) /* Bit 0: PECR and data EEPROM lock */
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# define FLASH_PECR_PRGLOCK (1 << 1) /* Bit 1: Program memory lock */
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# define FLASH_PECR_OPTLOCK (1 << 2) /* Bit 2: Option bytes block lock */
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# define FLASH_PECR_PROG (1 << 3) /* Bit 3: Program memory selection */
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# define FLASH_PECR_DATA (1 << 4) /* Bit 4: Data EEPROM selection */
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# define FLASH_PECR_FTDW (1 << 8) /* Bit 8: Fixed time data write for Byte, Half Word and Word programming */
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# define FLASH_PECR_ERASE (1 << 9) /* Bit 9: Page or Double Word erase mode */
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# define FLASH_PECR_FPRG (1 << 10) /* Bit 10: Half Page/Double Word programming mode */
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# define FLASH_PECR_PARALLBANK (1 << 15) /* Bit 15: Parallel bank mode */
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# define FLASH_PECR_EOPIE (1 << 16) /* Bit 16: End of programming interrupt enable */
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# define FLASH_PECR_ERRIE (1 << 17) /* Bit 17: Error interrupt enable */
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# define FLASH_PECR_OBL_LAUNCH (1 << 18) /* Bit 18: Launch the option byte loading */
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#endif
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/* Flash Control Register (CR) */
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@ -380,7 +452,6 @@
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# define FLASH_OPTCR1_BFB2_SHIFT (4) /* Bits 4: Dual-bank Boot option byte */
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# define FLASH_OPTCR1_BFB2_MASK (1 << FLASH_OPTCR_NWRP_SHIFT)
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#endif
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#if defined(CONFIG_STM32_STM32F446)
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@ -59,10 +59,10 @@
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#include "up_arch.h"
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/* Only for the STM32F[1|3|4]0xx family for now */
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/* Only for the STM32F[1|3|4]0xx family and STM32L15xx (EEPROM only) for now */
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
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defined (CONFIG_STM32_STM32F40XX)
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defined (CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
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#if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) && \
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(defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX))
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@ -73,15 +73,25 @@
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* Pre-processor Definitions
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************************************************************************************/
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#define FLASH_KEY1 0x45670123
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#define FLASH_KEY2 0xCDEF89AB
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#if defined(CONFIG_STM32_STM32L15XX)
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# define FLASH_KEY1 0x8C9DAEBF
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# define FLASH_KEY2 0x13141516
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#else
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# define FLASH_KEY1 0x45670123
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# define FLASH_KEY2 0xCDEF89AB
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#endif
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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#define FLASH_CR_PAGE_ERASE FLASH_CR_PER
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#define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPRT_ERR
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# define FLASH_CR_PAGE_ERASE FLASH_CR_PER
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# define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPRT_ERR
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#elif defined(CONFIG_STM32_STM32F40XX)
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#define FLASH_CR_PAGE_ERASE FLASH_CR_SER
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#define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPERR
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# define FLASH_CR_PAGE_ERASE FLASH_CR_SER
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# define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPERR
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#endif
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#if defined(CONFIG_STM32_STM32L15XX)
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# define EEPROM_KEY1 0x89ABCDEF
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# define EEPROM_KEY2 0x02030405
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#endif
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/************************************************************************************
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@ -107,6 +117,8 @@ static inline void sem_unlock(void)
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sem_post(&g_sem);
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}
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#if !defined(CONFIG_STM32_STM32L15XX)
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static void flash_unlock(void)
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{
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while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
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@ -128,6 +140,8 @@ static void flash_lock(void)
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modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
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}
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#endif /* !defined(CONFIG_STM32_STM32L15XX) */
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#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
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static void data_cache_disable(void)
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{
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@ -146,6 +160,183 @@ static void data_cache_enable(void)
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}
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#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */
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#if defined(CONFIG_STM32_STM32L15XX)
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static void stm32_eeprom_unlock(void)
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{
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while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
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{
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up_waste();
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}
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if (getreg32(STM32_FLASH_PECR) & FLASH_PECR_PELOCK)
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{
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/* Unlock sequence */
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putreg32(EEPROM_KEY1, STM32_FLASH_PEKEYR);
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putreg32(EEPROM_KEY2, STM32_FLASH_PEKEYR);
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}
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}
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static void stm32_eeprom_lock(void)
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{
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modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PELOCK);
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}
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static void flash_unlock(void)
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{
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if (getreg32(STM32_FLASH_PECR) & FLASH_PECR_PRGLOCK)
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{
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stm32_eeprom_unlock();
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/* Unlock sequence */
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putreg32(FLASH_KEY1, STM32_FLASH_PRGKEYR);
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putreg32(FLASH_KEY2, STM32_FLASH_PRGKEYR);
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}
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}
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static void flash_lock(void)
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{
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modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PRGLOCK);
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stm32_eeprom_lock();
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}
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static ssize_t stm32_eeprom_erase_write(size_t addr, const void *buf,
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size_t buflen)
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{
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const char *cbuf = buf;
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size_t i;
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if (buflen == 0)
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{
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return 0;
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}
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/* Check for valid address range */
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if (addr >= STM32_EEPROM_BASE)
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{
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addr -= STM32_EEPROM_BASE;
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}
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if (addr >= STM32_EEPROM_SIZE)
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{
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return -EINVAL;
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}
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/* TODO: Voltage range must be range 1 or 2. Erase/program not allowed in
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* range 3.
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*/
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stm32_eeprom_unlock();
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/* Clear pending status flags. */
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putreg32(FLASH_SR_WRPERR | FLASH_SR_PGAERR |
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FLASH_SR_SIZERR | FLASH_SR_OPTVERR |
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FLASH_SR_OPTVERRUSR | FLASH_SR_RDERR, STM32_FLASH_SR);
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/* Enable automatic erasing (by disabling 'fixed time' programming). */
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modifyreg32(STM32_FLASH_PECR, FLASH_PECR_FTDW, 0);
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/* Write buffer to EEPROM data memory. */
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addr += STM32_EEPROM_BASE;
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i = 0;
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while (i < buflen)
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{
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uint32_t writeval;
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size_t left = buflen - i;
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if ((addr & 0x03) == 0x00 && left >= 4)
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{
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/* Read/erase/write word */
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writeval = cbuf ? *(uint32_t *)cbuf : 0;
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putreg32(writeval, addr);
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}
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else if ((addr & 0x01) == 0x00 && left >= 2)
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{
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/* Read/erase/write half-word */
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writeval = cbuf ? *(uint16_t *)cbuf : 0;
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putreg16(writeval, addr);
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}
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else
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{
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/* Read/erase/write byte */
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writeval = cbuf ? *(uint8_t *)cbuf : 0;
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putreg8(writeval, addr);
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}
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/* ... and wait to complete. */
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while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
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{
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up_waste();
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}
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/* Verify */
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|
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/* We do not check Options Byte invalid flags FLASH_SR_OPTVERR
|
||||
* and FLASH_SR_OPTVERRUSR for EEPROM erase/write. They are unrelated
|
||||
* and STM32L standard library does not check for these either.
|
||||
*/
|
||||
|
||||
if (getreg32(STM32_FLASH_SR) & (FLASH_SR_WRPERR | FLASH_SR_PGAERR |
|
||||
FLASH_SR_SIZERR | FLASH_SR_RDERR))
|
||||
{
|
||||
stm32_eeprom_lock();
|
||||
return -EROFS;
|
||||
}
|
||||
|
||||
if ((addr & 0x03) == 0x00 && left >= 4)
|
||||
{
|
||||
if (getreg32(addr) != writeval)
|
||||
{
|
||||
stm32_eeprom_lock();
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
addr += 4;
|
||||
i += 4;
|
||||
cbuf += !!(cbuf) * 4;
|
||||
}
|
||||
else if ((addr & 0x01) == 0x00 && left >= 2)
|
||||
{
|
||||
if (getreg16(addr) != writeval)
|
||||
{
|
||||
stm32_eeprom_lock();
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
addr += 2;
|
||||
i += 2;
|
||||
cbuf += !!(cbuf) * 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (getreg8(addr) != writeval)
|
||||
{
|
||||
stm32_eeprom_lock();
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
addr += 1;
|
||||
i += 1;
|
||||
cbuf += !!(cbuf) * 1;
|
||||
}
|
||||
}
|
||||
|
||||
stm32_eeprom_lock();
|
||||
return buflen;
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_STM32_STM32L15XX) */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
@ -164,6 +355,35 @@ void stm32_flash_lock(void)
|
||||
sem_unlock();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX)
|
||||
|
||||
size_t stm32_eeprom_size(void)
|
||||
{
|
||||
return STM32_EEPROM_SIZE;
|
||||
}
|
||||
|
||||
size_t stm32_eeprom_getaddress(void)
|
||||
{
|
||||
return STM32_EEPROM_BASE;
|
||||
}
|
||||
|
||||
ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen)
|
||||
{
|
||||
if (!buf)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return stm32_eeprom_erase_write(addr, buf, buflen);
|
||||
}
|
||||
|
||||
ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen)
|
||||
{
|
||||
return stm32_eeprom_erase_write(addr, NULL, eraselen);
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_STM32_STM32L15XX) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||
size_t up_progmem_pagesize(size_t page)
|
||||
{
|
||||
@ -260,6 +480,8 @@ size_t up_progmem_getaddress(size_t page)
|
||||
|
||||
#endif /* def CONFIG_STM32_STM32F40XX */
|
||||
|
||||
#if !defined(CONFIG_STM32_STM32L15XX)
|
||||
|
||||
size_t up_progmem_npages(void)
|
||||
{
|
||||
return STM32_FLASH_NPAGES;
|
||||
@ -271,14 +493,14 @@ bool up_progmem_isuniform(void)
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif /* def STM32_FLASH_PAGESIZE */
|
||||
#endif
|
||||
}
|
||||
|
||||
ssize_t up_progmem_erasepage(size_t page)
|
||||
{
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||
size_t page_address;
|
||||
#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) */
|
||||
#endif
|
||||
|
||||
if (page >= STM32_FLASH_NPAGES)
|
||||
{
|
||||
@ -438,5 +660,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
|
||||
return written;
|
||||
}
|
||||
|
||||
#endif /* !defined(CONFIG_STM32_STM32L15XX) */
|
||||
|
||||
#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined (CONFIG_STM32_STM32F40XX) */
|
||||
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) */
|
||||
|
@ -46,4 +46,60 @@
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_flash.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_eeprom_size
|
||||
*
|
||||
* Description:
|
||||
* Get EEPROM data memory size
|
||||
*
|
||||
* Returns:
|
||||
* Length of EEPROM memory region
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
size_t stm32_eeprom_size(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_eeprom_getaddress
|
||||
*
|
||||
* Description:
|
||||
* Get EEPROM data memory address
|
||||
*
|
||||
* Returns:
|
||||
* Address of EEPROM memory region
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
size_t stm32_eeprom_getaddress(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_eeprom_write
|
||||
*
|
||||
* Description:
|
||||
* Write buffer to EEPROM data memory address
|
||||
*
|
||||
* Returns:
|
||||
* Number of written bytes or error code.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_eeprom_erase
|
||||
*
|
||||
* Description:
|
||||
* Erase memory on EEPROM data memory address
|
||||
*
|
||||
* Returns:
|
||||
* Number of erased bytes or error code.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */
|
||||
|
Loading…
Reference in New Issue
Block a user