From 9a32e907df2ed4a58f19e837ad2796e57322be5a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 21 Aug 2015 18:22:47 -0600 Subject: [PATCH] Trivial, cosmetic changes from review of merge --- arch/arm/src/stm32/chip/stm32f44xxx_otgfs.h | 2 +- arch/arm/src/stm32/stm32f42xxx_rcc.c | 16 ++++++------- arch/arm/src/stm32/stm32f44xxx_rcc.c | 26 ++++++++++----------- 3 files changed, 21 insertions(+), 23 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32f44xxx_otgfs.h b/arch/arm/src/stm32/chip/stm32f44xxx_otgfs.h index d193d56051..231c4b352c 100644 --- a/arch/arm/src/stm32/chip/stm32f44xxx_otgfs.h +++ b/arch/arm/src/stm32/chip/stm32f44xxx_otgfs.h @@ -1,7 +1,7 @@ /**************************************************************************************************** * arch/arm/src/stm32/chip/stm32f44xxx_otgfs.h * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/arch/arm/src/stm32/stm32f42xxx_rcc.c b/arch/arm/src/stm32/stm32f42xxx_rcc.c index c28435842f..b6082e44e7 100644 --- a/arch/arm/src/stm32/stm32f42xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f42xxx_rcc.c @@ -672,21 +672,21 @@ static void stm32_stdclockconfig(void) /* Set the HCLK source/divider */ - regval = getreg32(STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; regval |= STM32_RCC_CFGR_HPRE; putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; regval |= STM32_RCC_CFGR_PPRE2; putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); @@ -694,7 +694,7 @@ static void stm32_stdclockconfig(void) #ifdef CONFIG_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); putreg32(regval, STM32_RCC_CFGR); @@ -713,7 +713,7 @@ static void stm32_stdclockconfig(void) /* Enable the main PLL */ - regval = getreg32(STM32_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; putreg32(regval, STM32_RCC_CR); @@ -766,19 +766,19 @@ static void stm32_stdclockconfig(void) #ifdef CONFIG_STM32_LTDC /* Configure PLLSAI */ - regval = getreg32(STM32_RCC_PLLSAICFGR); + regval = getreg32(STM32_RCC_PLLSAICFGR); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN | STM32_RCC_PLLSAICFGR_PLLSAIR | STM32_RCC_PLLSAICFGR_PLLSAIQ); putreg32(regval, STM32_RCC_PLLSAICFGR); - regval = getreg32(STM32_RCC_DCKCFGR); + regval = getreg32(STM32_RCC_DCKCFGR); regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; putreg32(regval, STM32_RCC_DCKCFGR); /* Enable PLLSAI */ - regval = getreg32(STM32_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAION; putreg32(regval, STM32_RCC_CR); diff --git a/arch/arm/src/stm32/stm32f44xxx_rcc.c b/arch/arm/src/stm32/stm32f44xxx_rcc.c index dd3c7f10e0..903d4183af 100644 --- a/arch/arm/src/stm32/stm32f44xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f44xxx_rcc.c @@ -604,21 +604,21 @@ static void stm32_stdclockconfig(void) /* Set the HCLK source/divider */ - regval = getreg32(STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; regval |= STM32_RCC_CFGR_HPRE; putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; regval |= STM32_RCC_CFGR_PPRE2; putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); @@ -626,7 +626,7 @@ static void stm32_stdclockconfig(void) #ifdef CONFIG_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); putreg32(regval, STM32_RCC_CFGR); @@ -645,7 +645,7 @@ static void stm32_stdclockconfig(void) /* Enable the main PLL */ - regval = getreg32(STM32_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; putreg32(regval, STM32_RCC_CR); @@ -664,7 +664,7 @@ static void stm32_stdclockconfig(void) { } - regval = getreg32(STM32_PWR_CR); + regval = getreg32(STM32_PWR_CR); regval |= PWR_CR_ODSWEN; putreg32(regval, STM32_PWR_CR); while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0) @@ -697,7 +697,7 @@ static void stm32_stdclockconfig(void) /* Configure PLLSAI */ - regval = getreg32(STM32_RCC_PLLSAICFGR); + regval = getreg32(STM32_RCC_PLLSAICFGR); regval &= ~(RCC_PLLSAICFGR_PLLSAIM_MASK | RCC_PLLSAICFGR_PLLSAIN_MASK | RCC_PLLSAICFGR_PLLSAIP_MASK | @@ -708,7 +708,7 @@ static void stm32_stdclockconfig(void) | STM32_RCC_PLLSAICFGR_PLLSAIQ); putreg32(regval, STM32_RCC_PLLSAICFGR); - regval = getreg32(STM32_RCC_DCKCFGR); + regval = getreg32(STM32_RCC_DCKCFGR); regval &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MASK | RCC_DCKCFGR_PLLSAIDIVQ_MASK | RCC_DCKCFGR_SAI1SRC_MASK | @@ -728,7 +728,7 @@ static void stm32_stdclockconfig(void) /* Enable PLLSAI */ - regval = getreg32(STM32_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAION; putreg32(regval, STM32_RCC_CR); @@ -743,7 +743,7 @@ static void stm32_stdclockconfig(void) /* Configure PLLI2S */ - regval = getreg32(STM32_RCC_PLLI2SCFGR); + regval = getreg32(STM32_RCC_PLLI2SCFGR); regval &= ~(RCC_PLLI2SCFGR_PLLI2SM_MASK | RCC_PLLI2SCFGR_PLLI2SN_MASK | RCC_PLLI2SCFGR_PLLI2SP_MASK | @@ -755,7 +755,7 @@ static void stm32_stdclockconfig(void) | STM32_RCC_PLLI2SCFGR_PLLI2SR); putreg32(regval, STM32_RCC_PLLI2SCFGR); - regval = getreg32(STM32_RCC_DCKCFGR2); + regval = getreg32(STM32_RCC_DCKCFGR2); regval &= ~(RCC_DCKCFGR2_FMPI2C1SEL_MASK | RCC_DCKCFGR2_CECSEL_MASK | RCC_DCKCFGR2_CK48MSEL_MASK | @@ -771,7 +771,7 @@ static void stm32_stdclockconfig(void) /* Enable PLLI2S */ - regval = getreg32(STM32_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLI2SON; putreg32(regval, STM32_RCC_CR); @@ -782,8 +782,6 @@ static void stm32_stdclockconfig(void) } #endif - - #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK) /* Low speed internal clock source LSI */