Removed unused ARMv7-A cache function
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ae6ed8ca52
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@ -98,7 +98,6 @@
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.globl cp15_invalidate_dcache_for_dma
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.globl cp15_invalidate_dcache_for_dma
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.globl cp15_clean_dcache_for_dma
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.globl cp15_clean_dcache_for_dma
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.globl cp15_flush_dcache_for_dma
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.globl cp15_flush_dcache_for_dma
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.globl cp15_flush_kern_dcache_for_dma
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/****************************************************************************
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/****************************************************************************
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* Public Functions
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* Public Functions
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@ -302,44 +301,4 @@ cp15_flush_dcache_for_dma:
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dsb
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dsb
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bx lr
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bx lr
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.size cp15_flush_dcache_for_dma, . - cp15_flush_dcache_for_dma
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.size cp15_flush_dcache_for_dma, . - cp15_flush_dcache_for_dma
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/****************************************************************************
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* Name: cp15_flush_kern_dcache_for_dma
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*
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* Description:
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* Ensure that the data held in the page kaddr is written back to the page
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* in question.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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.globl cp15_flush_kern_dcache_for_dma
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.type cp15_flush_kern_dcache_for_dma, function
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cp15_flush_kern_dcache_for_dma:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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and r3, r3, #0xf
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mov r2, #4
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mov r2, r2, lsl r3 /* Get the cache line size in bytes */
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add r1, r0, r1
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sub r3, r2, #1 /* R3=Cache line size mask */
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bic r0, r0, r3 /* R0=aligned start address */
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mcrne CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
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add r0, r0, r2 /* R12=Next cache line */
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cmp r0, r1 /* Loop until all cache lines have been cleaned */
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blo 1b /* Merge with loop flushing each D cache line to memory */
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dsb
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bx lr
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.size cp15_flush_kern_dcache_for_dma, . - cp15_flush_kern_dcache_for_dma
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.end
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.end
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