arch/arm/src/tiva: Remove CONFIG_TIVA_BOARD_EARLYINIT. The option is no long meaningfule. Also set the CC13xx SYSCLCK freqency to a fixed 48MHz.
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@ -265,10 +265,6 @@ config LM_REVA2
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Some early silicon returned an increase LDO voltage or 2.75V to work
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Some early silicon returned an increase LDO voltage or 2.75V to work
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around a PLL bug
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around a PLL bug
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config TIVA_BOARD_EARLYINIT
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bool
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default n
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menu "Tiva/Stellaris Peripheral Support"
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menu "Tiva/Stellaris Peripheral Support"
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# MCU capabilities
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# MCU capabilities
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@ -218,12 +218,8 @@ void __start(void)
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/* Configure the UART so that we can get debug output as soon as possible */
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/* Configure the UART so that we can get debug output as soon as possible */
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#ifdef CONFIG_TIVA_BOARD_EARLYINIT
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board_earlyinit();
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#else
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up_clockconfig();
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up_clockconfig();
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up_lowsetup();
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up_lowsetup();
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#endif
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tiva_fpuconfig();
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tiva_fpuconfig();
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showprogress('A');
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showprogress('A');
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@ -75,19 +75,4 @@ extern const uintptr_t g_idle_topstack;
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void tiva_boardinitialize(void);
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void tiva_boardinitialize(void);
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/****************************************************************************
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* Name: board_earlyinit
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*
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* Description:
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* If CONFIG_TIVA_BOARD_EARLYINIT, then board-specific logic must provide
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* the function board_earlyinit() to provide very customized lower-level
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* board bringup. board_earlyinit() will be called by the start-up logic
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* instead of up_clockconfig() and up_lowsetup().
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*
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****************************************************************************/
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#ifdef CONFIG_TIVA_BOARD_EARLYINIT
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void board_earlyinit(void);
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#endif
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#endif /* __ARCH_ARM_SRC_TIVA_TIVA_START_H */
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#endif /* __ARCH_ARM_SRC_TIVA_TIVA_START_H */
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@ -92,7 +92,7 @@
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/* When the PLL is active, the system clock frequency (SysClk) is calculated using
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/* When the PLL is active, the system clock frequency (SysClk) is calculated using
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* the following equation:
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* the following equation:
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*
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*
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* SysClk = Fvco/ (sysdiv + 1)
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* SysClk = Fvco / (sysdiv + 1)
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*
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*
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* The following setup generates Sysclk = 120MHz:
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* The following setup generates Sysclk = 120MHz:
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*/
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*/
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