arch/arm/src/tiva: Remove CONFIG_TIVA_BOARD_EARLYINIT. The option is no long meaningfule. Also set the CC13xx SYSCLCK freqency to a fixed 48MHz.

This commit is contained in:
Gregory Nutt 2018-12-04 17:20:25 -06:00
parent c629d867e0
commit 9a68127e3e
4 changed files with 1 additions and 24 deletions

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@ -265,10 +265,6 @@ config LM_REVA2
Some early silicon returned an increase LDO voltage or 2.75V to work Some early silicon returned an increase LDO voltage or 2.75V to work
around a PLL bug around a PLL bug
config TIVA_BOARD_EARLYINIT
bool
default n
menu "Tiva/Stellaris Peripheral Support" menu "Tiva/Stellaris Peripheral Support"
# MCU capabilities # MCU capabilities

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@ -218,12 +218,8 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */ /* Configure the UART so that we can get debug output as soon as possible */
#ifdef CONFIG_TIVA_BOARD_EARLYINIT
board_earlyinit();
#else
up_clockconfig(); up_clockconfig();
up_lowsetup(); up_lowsetup();
#endif
tiva_fpuconfig(); tiva_fpuconfig();
showprogress('A'); showprogress('A');

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@ -75,19 +75,4 @@ extern const uintptr_t g_idle_topstack;
void tiva_boardinitialize(void); void tiva_boardinitialize(void);
/****************************************************************************
* Name: board_earlyinit
*
* Description:
* If CONFIG_TIVA_BOARD_EARLYINIT, then board-specific logic must provide
* the function board_earlyinit() to provide very customized lower-level
* board bringup. board_earlyinit() will be called by the start-up logic
* instead of up_clockconfig() and up_lowsetup().
*
****************************************************************************/
#ifdef CONFIG_TIVA_BOARD_EARLYINIT
void board_earlyinit(void);
#endif
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_START_H */ #endif /* __ARCH_ARM_SRC_TIVA_TIVA_START_H */

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@ -92,7 +92,7 @@
/* When the PLL is active, the system clock frequency (SysClk) is calculated using /* When the PLL is active, the system clock frequency (SysClk) is calculated using
* the following equation: * the following equation:
* *
* SysClk = Fvco/ (sysdiv + 1) * SysClk = Fvco / (sysdiv + 1)
* *
* The following setup generates Sysclk = 120MHz: * The following setup generates Sysclk = 120MHz:
*/ */