Tiva Ethernet: More progress with register bit definitions
This commit is contained in:
Gregory Nutt
parent
8cea115be7
commit
9a71dc091b
@ -391,92 +391,285 @@
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#define EMAC_STATUS_TXFE (1 << 24) /* Bit 24: TX/RX Controller TX FIFO Not Empty Status */
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#define EMAC_STATUS_TXFF (1 << 25) /* Bit 25: TX/RX Controller TX FIFO Full Status */
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/* Ethernet MAC Remote Wake-Up Frame Filter */
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#define EMAC_RWUFF_
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/* Ethernet MAC Remote Wake-Up Frame Filter (32-bit data) */
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/* Ethernet MAC PMT Control and Status Register */
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#define EMAC_PMTCTLSTAT_
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#define EMAC_PMTCTLSTAT_PWRDWN (1 << 0) /* Bit 0: Power Down */
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#define EMAC_PMTCTLSTAT_MGKPKTEN (1 << 1) /* Bit 1: Magic Packet Enable */
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#define EMAC_PMTCTLSTAT_WUPFREN (1 << 2) /* Bit 2: Wake-Up Frame Enable */
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#define EMAC_PMTCTLSTAT_MGKPRX (1 << 5) /* Bit 3: Magic Packet Received */
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#define EMAC_PMTCTLSTAT_WUPRX (1 << 6) /* Bit 6: Wake-Up Frame Received */
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#define EMAC_PMTCTLSTAT_GLBLUCAST (1 << 9) /* Bit 7: Global Unicast */
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#define EMAC_PMTCTLSTAT_RWKPTR_SHIFT (24) /* Bits 24-26: Remote Wake-Up FIFO Pointer */
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#define EMAC_PMTCTLSTAT_RWKPTR_MASK (7 << EMAC_PMTCTLSTAT_RWKPTR_SHIFT)
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# define EMAC_PMTCTLSTAT_RWKPTR(n) ((uint32_t)(n) << EMAC_PMTCTLSTAT_RWKPTR_SHIFT)
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#define EMAC_PMTCTLSTAT_WUPFRRST (1 << 31) /* Bit 31: Wake-Up Frame Filter Register Pointer Reset */
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/* Ethernet MAC Raw Interrupt Status */
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#define EMAC_RIS_
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#define EMAC_RIS_PMT (1 << 3) /* Bit 3: PMT Interrupt Status */
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#define EMAC_RIS_MMC (1 << 4) /* Bit 4: MMC Interrupt Status */
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#define EMAC_RIS_MMCRX (1 << 5) /* Bit 5: MMC Receive Interrupt Status */
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#define EMAC_RIS_MMCTX (1 << 6) /* Bit 6: MMC Transmit Interrupt Status */
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#define EMAC_RIS_TS (1 << 9) /* Bit 9: Timestamp Interrupt Status */
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/* Ethernet MAC Interrupt Mask */
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#define EMAC_IM_
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#define EMAC_IM_PMT (1 << 3) /* Bit 3: PMT Interrupt Mask */
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#define EMAC_IM_TSI (1 << 9) /* Bit 9: Timestamp Interrupt Mask */
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/* Ethernet MAC Address 0 High */
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#define EMAC_ADDR0H_
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/* Ethernet MAC Address 0 Low Register */
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#define EMAC_ADDR0L_
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/* Ethernet MAC Address 0 Low Register (32-bit MAC Address0 [31:0]) */
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#define EMAC_ADDR0H_ADDRHI_SHIFT (0) /* Bits 0-15: MAC Address0 [47:32] */
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#define EMAC_ADDR0H_ADDRHI_MASK (0xffff << EMAC_ADDR0H_ADDRHI_SHIFT)
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# define EMAC_ADDR0H_ADDRHI(n) ((uint32_t)(n) << EMAC_ADDR0H_ADDRHI_SHIFT)
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#define EMAC_ADDR0H_AE (1 << 31) /* Bit 31: Address Enable */
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/* Ethernet MAC Address 1 High */
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#define EMAC_ADDR1H_
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/* Ethernet MAC Address 1 Low */
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#define EMAC_ADDR1L_
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/* Ethernet MAC Address 1 Low (32-bit MAC Address0 [31:0]) */
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#define EMAC_ADDR1H_ADDRHI_SHIFT (0) /* Bits 0-15: MAC Address0 [47:32] */
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#define EMAC_ADDR1H_ADDRHI_MASK (0xffff << EMAC_ADDR1H_ADDRHI_SHIFT)
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# define EMAC_ADDR1H_ADDRHI(n) ((uint32_t)(n) << EMAC_ADDR1H_ADDRHI_SHIFT)
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#define EMAC_ADDR1H_MBC_SHIFT (24) /* Bits 24-29: Mask Byte Control */
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#define EMAC_ADDR1H_MBC_MASK (0x3f << EMAC_ADDR1H_MBC_SHIFT)
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# define EMAC_ADDR1H_MBC(n) ((uint32_t)(n) << EMAC_ADDR1H_MBC_SHIFT)
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# define EMAC_ADDR1H_EMACADDR1L_0 (1 << 24) /* ADDRLO [7:0] of EMACADDR1L register */
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# define EMAC_ADDR1H_EMACADDR1L_8 (1 << 25) /* ADDRLO [15:8] of EMACADDR1L register */
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# define EMAC_ADDR1H_EMACADDR1L_16 (1 << 26) /* ADDRLO [23:16] of EMACADDR1L register */
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# define EMAC_ADDR1H_EMACADDR1L_24 (1 << 27) /* ADDRLO [31:24] of EMACADDR1L register */
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# define EMAC_ADDR1H_EMACADDR1H_0 (1 << 28) /* ADDRHI [7:0] of EMACADDR1H */
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# define EMAC_ADDR1H_EMACADDR1H_8 (1 << 29) /* ADDRHI [15:8] of EMACADDR1H Register */
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#define EMAC_ADDR1H_SA (1 << 30) /* Bit 30: Source Address */
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#define EMAC_ADDR1H_AE (1 << 31) /* Bit 31: Address Enable */
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/* Ethernet MAC Address 2 High */
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#define EMAC_ADDR2H_
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/* Ethernet MAC Address 2 Low */
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#define EMAC_ADDR2L_
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/* Ethernet MAC Address 2 Low (32-bit MAC Address0 [31:0]) */
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#define EMAC_ADDR2H_ADDRHI_SHIFT (0) /* Bits 0-15: MAC Address0 [47:32] */
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#define EMAC_ADDR2H_ADDRHI_MASK (0xffff << EMAC_ADDR2H_ADDRHI_SHIFT)
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# define EMAC_ADDR2H_ADDRHI(n) ((uint32_t)(n) << EMAC_ADDR2H_ADDRHI_SHIFT)
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#define EMAC_ADDR2H_MBC_SHIFT (24) /* Bits 24-29: Mask Byte Control */
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#define EMAC_ADDR2H_MBC_MASK (0x3f << EMAC_ADDR2H_MBC_SHIFT)
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# define EMAC_ADDR2H_MBC(n) ((uint32_t)(n) << EMAC_ADDR2H_MBC_SHIFT)
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# define EMAC_ADDR2H_EMACADDR2L_0 (1 << 24) /* ADDRLO [7:0] of EMACADDR2L register */
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# define EMAC_ADDR2H_EMACADDR2L_8 (1 << 25) /* ADDRLO [15:8] of EMACADDR2L register */
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# define EMAC_ADDR2H_EMACADDR2L_16 (1 << 26) /* ADDRLO [23:16] of EMACADDR2L register */
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# define EMAC_ADDR2H_EMACADDR2L_24 (1 << 27) /* ADDRLO [31:24] of EMACADDR2L register */
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# define EMAC_ADDR2H_EMACADDR2H_0 (1 << 28) /* ADDRHI [7:0] of EMACADDR2H */
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# define EMAC_ADDR2H_EMACADDR2H_8 (1 << 29) /* ADDRHI [15:8] of EMACADDR2H Register */
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#define EMAC_ADDR2H_SA (1 << 30) /* Bit 30: Source Address */
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#define EMAC_ADDR2H_AE (1 << 31) /* Bit 31: Address Enable */
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/* Ethernet MAC Address 3 High */
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#define EMAC_ADDR3H_
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/* Ethernet MAC Address 3 Low */
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#define EMAC_ADDR3L_
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/* Ethernet MAC Address 3 Low (32-bit MAC Address0 [31:0]) */
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#define EMAC_ADDR3H_ADDRHI_SHIFT (0) /* Bits 0-15: MAC Address0 [47:32] */
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#define EMAC_ADDR3H_ADDRHI_MASK (0xffff << EMAC_ADDR3H_ADDRHI_SHIFT)
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# define EMAC_ADDR3H_ADDRHI(n) ((uint32_t)(n) << EMAC_ADDR3H_ADDRHI_SHIFT)
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#define EMAC_ADDR3H_MBC_SHIFT (24) /* Bits 24-29: Mask Byte Control */
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#define EMAC_ADDR3H_MBC_MASK (0x3f << EMAC_ADDR3H_MBC_SHIFT)
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# define EMAC_ADDR3H_MBC(n) ((uint32_t)(n) << EMAC_ADDR3H_MBC_SHIFT)
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# define EMAC_ADDR3H_EMACADDR3L_0 (1 << 24) /* ADDRLO [7:0] of EMACADDR3L register */
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# define EMAC_ADDR3H_EMACADDR3L_8 (1 << 25) /* ADDRLO [15:8] of EMACADDR3L register */
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# define EMAC_ADDR3H_EMACADDR3L_16 (1 << 26) /* ADDRLO [23:16] of EMACADDR3L register */
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# define EMAC_ADDR3H_EMACADDR3L_24 (1 << 27) /* ADDRLO [31:24] of EMACADDR3L register */
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# define EMAC_ADDR3H_EMACADDR3H_0 (1 << 28) /* ADDRHI [7:0] of EMACADDR3H */
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# define EMAC_ADDR3H_EMACADDR3H_8 (1 << 29) /* ADDRHI [15:8] of EMACADDR3H Register */
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#define EMAC_ADDR3H_SA (1 << 30) /* Bit 30: Source Address */
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#define EMAC_ADDR3H_AE (1 << 31) /* Bit 31: Address Enable */
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/* Ethernet MAC Watchdog Timeout */
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#define EMAC_WDOGTO_
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#define EMAC_WDOGTO_WTO_SHIFT (0) /* Bits 0-13: Watchdog Timeout */
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#define EMAC_WDOGTO_WTO_MASK (0x3fff << EMAC_WDOGTO_WTO_SHIFT)
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# define EMAC_WDOGTO_WTO(n) ((uint32_t)(n) << EMAC_WDOGTO_WTO_SHIFT)
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#define EMAC_WDOGTO_PWE (1 << 16) /* Bit 16: Programmable Watchdog Enable */
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/* Ethernet MAC MMC Control */
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#define EMAC_MMCCTRL_
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#define EMAC_MMCCTRL_CNTRST (1 << 0) /* Bit 0: Counters Reset */
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#define EMAC_MMCCTRL_CNTSTPRO (1 << 1) /* Bit 1: Counters Stop Rollover */
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#define EMAC_MMCCTRL_RSTONRD (1 << 2) /* Bit 2: Reset on Read */
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#define EMAC_MMCCTRL_CNTFREEZ (1 << 3) /* Bit 3: MMC Counter Freeze */
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#define EMAC_MMCCTRL_CNTPRST (1 << 4) /* Bit 4: Counters Preset */
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#define EMAC_MMCCTRL_CNTPRSTLVL (1 << 5) /* Bit 5: Full/Half Preset Level Value */
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#define EMAC_MMCCTRL_UCDBC (1 << 8) /* Bit 8: Update MMC Counters for Dropped Broadcast Frames */
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/* Ethernet MAC MMC Receive Raw Interrupt Status */
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#define EMAC_MMCRXRIS_
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#define EMAC_MMCRXRIS_GBF (1 << 0) /* Bit 0: MMC Receive Good Bad Frame Counter Interrupt Status */
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#define EMAC_MMCRXRIS_CRCERR (1 << 5) /* Bit 5: MMC Receive CRC Error Frame Counter Interrupt Status */
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#define EMAC_MMCRXRIS_ALGNERR (1 << 6) /* Bit 6: MMC Receive Alignment Error Frame Counter Interrupt Status */
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#define EMAC_MMCRXRIS_UCGF (1 << 17) /* Bit 17: MMC Receive Unicast Good Frame Counter Interrupt Status */
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/* Ethernet MAC MMC Transmit Raw Interrupt Status */
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#define EMAC_MMCTXRIS_
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#define EMAC_MMCTXRIS_GBF (1 << 1) /* Bit 1: MMC Transmit Good Bad Frame Counter Interrupt Status */
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#define EMAC_MMCTXRIS_SCOLLGF (1 << 14) /* Bit 14: MMC Transmit Single Collision Good Frame Counter Interrupt Status */
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#define EMAC_MMCTXRIS_MCOLLGF (1 << 15) /* Bit 15: MMC Transmit Multiple Collision Good Frame Counter Interrupt Status */
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#define EMAC_MMCTXRIS_OCTCNT (1 << 20) /* Bit 20: Octet Counter Interrupt Status */
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/* Ethernet MAC MMC Receive Interrupt Mask */
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#define EMAC_MMCRXIM_
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#define EMAC_MMCRXIM_GBF (1 << 0) /* Bit 0: MMC Receive Good Bad Frame Counter Interrupt Mask */
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#define EMAC_MMCRXIM_CRCERR (1 << 5) /* Bit 5: MMC Receive CRC Error Frame Counter Interrupt Mask */
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#define EMAC_MMCRXIM_ALGNERR (1 << 6) /* Bit 6: MMC Receive Alignment Error Frame Counter Interrupt Mask */
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#define EMAC_MMCRXIM_UCGF (1 << 17) /* Bit 17: MMC Receive Unicast Good Frame Counter Interrupt Mask */
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/* Ethernet MAC MMC Transmit Interrupt Mask */
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#define EMAC_MMCTXIM_
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/* Ethernet MAC Transmit Frame Count for Good and Bad Frames */
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#define EMAC_TXCNTGB_
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/* Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision */
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#define EMAC_TXCNTSCOL_
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/* Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions */
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#define EMAC_TXCNTMCOL_
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/* Ethernet MAC Transmit Octet Count Good */
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#define EMAC_TXOCTCNTG_
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/* Ethernet MAC Receive Frame Count for Good and Bad Frames */
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#define EMAC_RXCNTGB_
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/* Ethernet MAC Receive Frame Count for CRC Error Frames */
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#define EMAC_RXCNTCRCERR_
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/* Ethernet MAC Receive Frame Count for Alignment Error Frames */
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#define EMAC_RXCNTALGNERR_
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/* Ethernet MAC Receive Frame Count for Good Unicast Frames */
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#define EMAC_RXCNTGUNI_
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#define EMAC_MMCTXIM_GBF (1 << 1) /* Bit 1: MMC Transmit Good Bad Frame Counter Interrupt Mask */
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#define EMAC_MMCTXIM_SCOLLGF (1 << 14) /* Bit 14: MMC Transmit Single Collision Good Frame Counter Interrupt Mask */
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#define EMAC_MMCTXIM_MCOLLGF (1 << 15) /* Bit 15: MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask */
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#define EMAC_MMCTXIM_OCTCNT (1 << 20) /* Bit 20: MMC Transmit Good Octet Counter Interrupt Mask */
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/* Ethernet MAC Transmit Frame Count for Good and Bad Frames (32-bit data) */
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/* Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision (32-bit data) */
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/* Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions (32-bit data) */
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/* Ethernet MAC Transmit Octet Count Good (32-bit data) */
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/* Ethernet MAC Receive Frame Count for Good and Bad Frames (32-bit data) */
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/* Ethernet MAC Receive Frame Count for CRC Error Frames (32-bit data) */
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/* Ethernet MAC Receive Frame Count for Alignment Error Frames (32-bit data) */
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/* Ethernet MAC Receive Frame Count for Good Unicast Frames (32-bit data) */
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/* Ethernet MAC VLAN Tag Inclusion or Replacement */
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#define EMAC_VLNINCREP_
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#define EMAC_VLNINCREP_VLT_SHIFT (0) /* Bits 0-15: VLAN Tag for Transmit Frames */
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#define EMAC_VLNINCREP_VLT_MASK (0xffff << EMAC_VLNINCREP_VLT_SHIFT)
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# define EMAC_VLNINCREP_VLT(n) ((uint32_t)(n) << EMAC_VLNINCREP_VLT_SHIFT)
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#define EMAC_VLNINCREP_VLC_SHIFT (16) /* Bits 16-17: VLAN Tag Control in Transmit Frames */
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#define EMAC_VLNINCREP_VLC_MASK (3 << EMAC_VLNINCREP_VLC_SHIFT)
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# define EMAC_VLNINCREP_VLC_NONE (0 << EMAC_VLNINCREP_VLC_SHIFT) /* No VLAN tag deletion, insertion, or replacement */
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# define EMAC_VLNINCREP_VLC_TAGDEL (1 << EMAC_VLNINCREP_VLC_SHIFT) /* VLAN tag deletion */
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# define EMAC_VLNINCREP_VLC_TAGINS (2 << EMAC_VLNINCREP_VLC_SHIFT) /* VLAN tag insertion */
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# define EMAC_VLNINCREP_VLC_TAGREP (3 << EMAC_VLNINCREP_VLC_SHIFT) /* VLAN tag replacement */
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#define EMAC_VLNINCREP_VLP (1 << 18) /* Bit 18: VLAN Priority Control */
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#define EMAC_VLNINCREP_CSVL (1 << 19) /* Bit 19: C-VLAN or S-VLAN */
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/* Ethernet MAC VLAN Hash Table */
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#define EMAC_VLANHASH_
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#define EMAC_VLANHASH_VLHT_SHIFT (0) /* Bits 0-15: VLAN Hash Table */
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#define EMAC_VLANHASH_VLHT_MASK (0xffff << EMAC_VLANHASH_VLHT_SHIFT)
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/* Ethernet MAC Timestamp Control */
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#define EMAC_TIMSTCTRL_
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#define EMAC_TIMSTCTRL_TSEN (1 << 0) /* Bit 0: Timestamp Enable */
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#define EMAC_TIMSTCTRL_TSFCUPDT (1 << 1) /* Bit 1: Timestamp Fine or Coarse Update */
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#define EMAC_TIMSTCTRL_TSINIT (1 << 2) /* Bit 2: Timestamp Initialize */
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#define EMAC_TIMSTCTRL_TSUPDT (1 << 3) /* Bit 3: Timestamp Update */
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#define EMAC_TIMSTCTRL_INTTRIG (1 << 4) /* Bit 4: Timestamp Interrupt Trigger Enable */
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#define EMAC_TIMSTCTRL_ADDREGUP (1 << 5) /* Bit 5: Addend Register Update */
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#define EMAC_TIMSTCTRL_ALLF (1 << 8) /* Bit 8: Enable Timestamp For All Frames */
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#define EMAC_TIMSTCTRL_DGTLBIN (1 << 9) /* Bit 9: Timestamp Digital or Binary Rollover Control */
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#define EMAC_TIMSTCTRL_PTPVER2 (1 << 10) /* Bit 10: Enable PTP Packet Processing For Version 2 Format */
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#define EMAC_TIMSTCTRL_PTPETH (1 << 11) /* Bit 11: Enable Processing of PTP Over Ethernet Frames */
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#define EMAC_TIMSTCTRL_PTPIPV6 (1 << 12) /* Bit 12: Enable Processing of PTP Frames Sent Over IPv6-UDP */
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#define EMAC_TIMSTCTRL_PTPIPV4 (1 << 13) /* Bit 13: Enable Processing of PTP Frames Sent over IPv4-UDP */
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#define EMAC_TIMSTCTRL_TSEVNT (1 << 14) /* Bit 14: Enable Timestamp Snapshot for Event Messages */
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#define EMAC_TIMSTCTRL_TSMAST (1 << 15) /* Bit 15: Enable Snapshot for Messages Relevant to Master */
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#define EMAC_TIMSTCTRL_SELPTP_SHIFT (16) /* Bits 16-17: Select PTP packets for Taking Snapshots */
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#define EMAC_TIMSTCTRL_SELPTP_MASK (3 << EMAC_TIMSTCTRL_SELPTP_SHIFT)
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# define EMAC_TIMSTCTRL_SELPTP(n) ((uint32_t)(n) << EMAC_TIMSTCTRL_SELPTP_SHIFT)
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#define EMAC_TIMSTCTRL_PTPFLTR (1 << 18) /* Bit 18: Enable MAC address for PTP Frame Filtering */
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/* Ethernet MAC Sub-Second Increment */
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#define EMAC_SUBSECINC_
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/* Ethernet MAC System Time - Seconds */
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#define EMAC_TIMSEC_
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#define EMAC_SUBSECINC_SSINC_SHIFT (0) /* Bits 0-7: Sub-second Increment Value */
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#define EMAC_SUBSECINC_SSINC_MASK (0xff << EMAC_SUBSECINC_SSINC_SHIFT)
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/* Ethernet MAC System Time - Seconds (32-bit value) */
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/* Ethernet MAC System Time - Nanoseconds */
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#define EMAC_TIMNANO_
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/* Ethernet MAC System Time - Seconds Update */
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#define EMAC_TIMSECU_
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#define EMAC_TIMNANO_TSSS_SHIFT (0) /* Bits 0-30: Timestamp Sub-Seconds */
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#define EMAC_TIMNANO_TSSS_MASK (0x7fffffff << EMAC_TIMNANO_TSSS_SHIFT)
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/* Ethernet MAC System Time - Seconds Update (32-bit value) */
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/* Ethernet MAC System Time - Nanoseconds Update */
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#define EMAC_TIMNANOU_
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/* Ethernet MAC Timestamp Addend */
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#define EMAC_TIMADD_
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/* Ethernet MAC Target Time Seconds */
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#define EMAC_TARGSEC_
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#define EMAC_TIMNANOU_TSSS_SHIFT (0) /* Bits 0-30: Timestamp Sub-Second */
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#define EMAC_TIMNANOU_TSSS_MASK (0x7fffffff << EMAC_TIMNANOU_TSSS_SHIFT)
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#define EMAC_TIMNANOU_ADDSUB (1 << 31) /* Bit 31: Add or subtract time */
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/* Ethernet MAC Timestamp Addend (32-bit value) */
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/* Ethernet MAC Target Time Seconds (32-bit value) */
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/* Ethernet MAC Target Time Nanoseconds */
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#define EMAC_TARGNANO_
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#define EMAC_TARGNANO_TTSLO_SHIFT (0) /* Bits 0-30: Target Timestamp Low Register */
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#define EMAC_TARGNANO_TTSLO_MASK (0x7fffffff << EMAC_TARGNANO_TTSLO_SHIFT)
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#define EMAC_TARGNANO_TRGTBUSY (1 << 31) /* Bit 31: Target Time Register Busy */
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/* Ethernet MAC System Time-Higher Word Seconds */
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#define EMAC_HWORDSEC_
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#define EMAC_HWORDSEC_TSHWR_SHIFT (0) /* Bits 0-15: Target Timestamp Higher Word Register */
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#define EMAC_HWORDSEC_TSHWR_MASK (0xffff << EMAC_HWORDSEC_TSHWR_SHIFT)
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/* Ethernet MAC Timestamp Status */
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#define EMAC_TIMSTAT_
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#define EMAC_TIMSTAT_TSSOVF (1 << 0) /* Bit 0: Timestamp Seconds Overflow */
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#define EMAC_TIMSTAT_TSTARGT (1 << 1) /* Bit 1: Timestamp Target Time Reached */
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/* Ethernet MAC PPS Control */
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#define EMAC_PPSCTRL_
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/* Ethernet MAC PPS0 Interval */
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#define EMAC_PPS0INTVL_
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/* Ethernet MAC PPS0 Width */
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#define EMAC_PPS0WIDTH_
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#define EMAC_PPSCTRL_PPSCTRL_SHIFT (0) /* Bits 0-3: EN0PPS Output Frequency Control (PPSCTRL) or Command Control (PPSCMD) */
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#define EMAC_PPSCTRL_PPSCTRL_MASK (15 << EMAC_PPSCTRL_PPSCTRL_SHIFT)
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# define EMAC_PPSCTRL_PPSCTRL_1HZ (0 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* EN0PPS signal=PTP reference clock/sec */
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# define EMAC_PPSCTRL_PPSCTRL_2HZ (1 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=2 Hz; digital rollover=1 Hz */
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# define EMAC_PPSCTRL_PPSCTRL_4HZ (2 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=4 Hz; digital rollover=2 Hz */
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# define EMAC_PPSCTRL_PPSCTRL_8HZ (3 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=8 Hz; digital rollover=4 Hz, */
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# define EMAC_PPSCTRL_PPSCTRL_16HZ (4 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=16 Hz; digital rollover=8 Hz */
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# define EMAC_PPSCTRL_PPSCTRL_32HZ (5 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=32 Hz; digital rollover=16 Hz */
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# define EMAC_PPSCTRL_PPSCTRL_64HZ (6 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=64 Hz; digital rollover=32 Hz */
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# define EMAC_PPSCTRL_PPSCTRL_128HZ (7 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=128 Hz; digital rollover=64 Hz */
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# define EMAC_PPSCTRL_PPSCTRL_256HZ (8 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* binary rollover=256 Hz; digital rollover=128 Hz */
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# define EMAC_PPSCTRL_PPSCTRL_512HZ (9 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* binary rollover=512 Hz; digital rollover=256 Hz */
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# define EMAC_PPSCTRL_PPSCTRL_1024HZ (10 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* binary rollover=1.024 kHz; digital rollover=512 Hz */
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# define EMAC_PPSCTRL_PPSCTRL_2048HZ (11 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=2.048 kHz; digital rollover=1.024 kHz */
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# define EMAC_PPSCTRL_PPSCTRL_4096HZ (12 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=4.096 kHz; digital rollover=2.048 kHz */
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# define EMAC_PPSCTRL_PPSCTRL_8192HZ (13 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=8.192 kHz; digital rollover=4.096 kHz */
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# define EMAC_PPSCTRL_PPSCTRL_16384HZ (14 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=16.384 kHz; digital rollover=8.092 kHz */
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# define EMAC_PPSCTRL_PPSCTRL_32768HZ (15 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=32.768 KHz; digital rollover=16.384 KHz */
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#define EMAC_PPSCTRL_PPSEN0 (1 << 4) /* Bit 4: Flexible PPS Output Mode Enable */
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#define EMAC_PPSCTRL_TRGMODS0_SHIFT (5) /* Bits 5-6: Target Time Register Mode for PPS0 Output */
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#define EMAC_PPSCTRL_TRGMODS0_MASK (3 << EMAC_PPSCTRL_TRGMODS0_SHIFT)
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# define EMAC_PPSCTRL_TRGMODS0_INTONLY (0 << EMAC_PPSCTRL_TRGMODS0_SHIFT) /* Generate the interrupt event */
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# define EMAC_PPSCTRL_TRGMODS0_INTPPS0 (2 << EMAC_PPSCTRL_TRGMODS0_SHIFT) /* Generate the interrupt event and control EN0PPS */
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# define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY (3 << EMAC_PPSCTRL_TRGMODS0_SHIFT) /* Control ENOPPS output */
|
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|
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/* Ethernet MAC PPS0 Interval (32-bit value) */
|
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/* Ethernet MAC PPS0 Width (32-bit value) */
|
||||
|
||||
/* Ethernet MAC DMA Bus Mode */
|
||||
#define EMAC_DMABUSMOD_
|
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|
||||
#define EMAC_DMABUSMOD_SWR (1 << 0) /* Bit 0: DMA Software Reset */
|
||||
#define EMAC_DMABUSMOD_DA (1 << 1) /* Bit 1: DMA Arbitration Scheme */
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||||
#define EMAC_DMABUSMOD_DSL_SHIFT (2) /* Bits 2-6: Descriptor Skip Length */
|
||||
#define EMAC_DMABUSMOD_DSL_MASK (31 << EMAC_DMABUSMOD_DSL_SHIFT)
|
||||
# define EMAC_DMABUSMOD_DSL(n) ((uint32_t)(n) << EMAC_DMABUSMOD_DSL_SHIFT)
|
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#define EMAC_DMABUSMOD_ATDS (1 << 7) /* Bit 7: Alternate Descriptor Size */
|
||||
#define EMAC_DMABUSMOD_PBL_SHIFT (8) /* Bits 8-13: Programmable Burst Length */
|
||||
#define EMAC_DMABUSMOD_PBL_MASK (0x3f << EMAC_DMABUSMOD_PBL_SHIFT)
|
||||
# define EMAC_DMABUSMOD_PBL(n) ((uint32_t)(n) << EMAC_DMABUSMOD_PBL_SHIFT)
|
||||
#define EMAC_DMABUSMOD_PR_SHIFT (14) /* Bits 14-15: Priority Ratio */
|
||||
#define EMAC_DMABUSMOD_PR_MASK (3 << EMAC_DMABUSMOD_PR_SHIFT)
|
||||
# define EMAC_DMABUSMOD_PR_11 (0 << EMAC_DMABUSMOD_PR_SHIFT) /* Priority Ratio is 1:1 */
|
||||
# define EMAC_DMABUSMOD_PR_21 (1 << EMAC_DMABUSMOD_PR_SHIFT) /* Priority Ratio is 2:1 */
|
||||
# define EMAC_DMABUSMOD_PR_31 (2 << EMAC_DMABUSMOD_PR_SHIFT) /* Priority Ratio is 3:1 */
|
||||
# define EMAC_DMABUSMOD_PR_41 (3 << EMAC_DMABUSMOD_PR_SHIFT) /* Priority Ratio is 4:1 */
|
||||
#define EMAC_DMABUSMOD_FB (1 << 16) /* Bit 16: Fixed Burst */
|
||||
#define EMAC_DMABUSMOD_RPBL_SHIFT (17) /* Bits 17:22: RX DMA Programmable Burst Length (PBL) */
|
||||
#define EMAC_DMABUSMOD_RPBL_MASK (0x3f << EMAC_DMABUSMOD_RPBL_SHIFT)
|
||||
# define EMAC_DMABUSMOD_RPBL(n) ((uint32_t)(n) << EMAC_DMABUSMOD_RPBL_SHIFT)
|
||||
#define EMAC_DMABUSMOD_USP (1 << 23) /* Bit 23: Use Separate Programmable Burst Length (PBL) */
|
||||
#define EMAC_DMABUSMOD_8XPBL (1 << 24) /* Bit 24: 8 x Programmable Burst Length (PBL) Mode */
|
||||
#define EMAC_DMABUSMOD_AAL (1 << 25) /* Bit 25: Address Aligned Beats */
|
||||
#define EMAC_DMABUSMOD_MB (1 << 26) /* Bit 26: Mixed Burst */
|
||||
#define EMAC_DMABUSMOD_TXPR (1 << 27) /* Bit 27: Transmit Priority */
|
||||
#define EMAC_DMABUSMOD_RIB (1 << 31) /* Bit 31: Rebuild Burst */
|
||||
|
||||
/* Ethernet MAC Transmit Poll Demand */
|
||||
#define EMAC_TXPOLLD_
|
||||
/* Ethernet MAC Receive Poll Demand */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user