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SAMA5: The ostest configuration have been converted to run out of NOR flash. There is more to be done, however

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This commit is contained in:
Gregory Nutt 2013-07-28 15:07:35 -06:00
parent 7dc8dd4b50
commit 9a94a3707c
15 changed files with 313 additions and 91 deletions
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4
ChangeLog
View File

@ -5209,4 +5209,6 @@
to simplify bring up of the SAMA5 (it will probably be removed
later) (2013-7-26).
* The sama5d3x-ek/hello now runs correctly (2013-7-28).
* configs/sama5d3x-ek/ostest/: This configuration has been modified
to run out NOR flash. More work is still needed to reconfigure the
SMC so the the NOR flash can work with the high clock (2013-7-28).

84
arch/Kconfig
View File

@ -194,34 +194,6 @@ config ARCH_CALIBRATION
watch to measure the actual delay then adjust BOARD_LOOPSPERMSEC until
the actual delay is 100 seconds.
config RAM_START
hex "Primary RAM start address (physical)"
default 0x0
help
The physical start address of primary installed RAM. "Primary" RAM
refers to the RAM that you link program code into. If program code
does not excecute out of RAM but from FLASH, then you may designate
any block of RAM as "primary."
config RAM_VSTART
hex "Primary RAM start address (virtual)"
default 0x0
depends on ARCH_HAVE_MMU
help
The virtual start address of installed primary RAM. "Primary" RAM
refers to the RAM that you link program code into. If program code
does not excecute out of RAM but from FLASH, then you may designate
any block of RAM as "primary."
config RAM_SIZE
int "Primary RAM size"
default 0
help
The size in bytes of the installed primary RAM. "Primary" RAM
refers to the RAM that you link program code into. If program code
does not excecute out of RAM but from FLASH, then you may designate
any block of RAM as "primary."
config ARCH_HAVE_INTERRUPTSTACK
bool
@ -269,3 +241,59 @@ config BOOT_COPYTORAM
RAM for better performance.
endchoice
menu "Boot Memory Configuration"
config RAM_START
hex "Primary RAM start address (physical)"
default 0x0
help
The physical start address of primary installed RAM. "Primary" RAM
refers to the RAM that you link program code into. If program code
does not excecute out of RAM but from FLASH, then you may designate
any block of RAM as "primary."
config RAM_VSTART
hex "Primary RAM start address (virtual)"
default 0x0
depends on ARCH_HAVE_MMU
help
The virtual start address of installed primary RAM. "Primary" RAM
refers to the RAM that you link program code into. If program code
does not excecute out of RAM but from FLASH, then you may designate
any block of RAM as "primary."
config RAM_SIZE
int "Primary RAM size"
default 0
help
The size in bytes of the installed primary RAM. "Primary" RAM
refers to the RAM that you link program code into. If program code
does not excecute out of RAM but from FLASH, then you may designate
any block of RAM as "primary."
if BOOT_RUNFROMFLASH && ARCH_HAVE_MMU
config FLASH_START
hex "Boot FLASH start address (physical)"
default 0x0
help
The physical start address of installed boot FLASH. "Boot" FLASH
refers to the FLASH that you link program code into.
config FLASH_VSTART
hex "Boot FLASH start address (virtual)"
default 0x0
help
The virtual start address of installed boot FLASH. "Boot" FLASH
refers to the FLASH that you link program code into.
config FLASH_SIZE
int "Boot FLASH size"
default 0
help
The size in bytes of the installed boot FLASH. "Boot" FLASH
refers to the FLASH that you link program code into.
endif
endmenu

71
arch/arm/src/armv7-a/arm_head.S
View File

@ -44,6 +44,8 @@
# include "pg_macros.h"
#endif
#include <arch/board/board.h>
#include "arm.h"
#include "cp15.h"
#include "sctlr.h"
@ -55,7 +57,6 @@
**********************************************************************************/
#undef ALIGNMENT_TRAP
#undef CPU_DCACHE_WRITETHROUGH
#undef CPU_CACHE_ROUND_ROBIN
#undef CPU_DCACHE_DISABLE
#undef CPU_ICACHE_DISABLE
@ -71,7 +72,6 @@
*/
#ifdef CONFIG_BOOT_RUNFROMFLASH
# error "Configuration not implemented"
# define DO_SDRAM_INIT 1
/* Check for the identity mapping: For this configuration, this would be
@ -163,10 +163,11 @@
****************************************************************************/
/* RX_NSECTIONS determines the number of 1Mb sections to map for the
* Read/eXecute address region. This is based on CONFIG_RAM_SIZE.
* Read/eXecute address region. This is based on NUTTX_TEXT_SIZE.
*/
#define RX_NSECTIONS ((CONFIG_RAM_SIZE+0x000fffff) >> 20)
#define RX_NSECTIONS ((NUTTX_TEXT_SIZE+0x000fffff) >> 20)
#define WR_NSECTIONS ((NUTTX_RAM_SIZE+0x000fffff) >> 20)
/****************************************************************************
* Assembly Macros
@ -393,14 +394,6 @@ __start:
mcr CP15_TTBCR(r0)
/* Enable DCache write-through if so configured.
*
* The Cortex-A5 MPCore data cache only supports a write-back policy.
*/
#ifdef CPU_DCACHE_WRITETHROUGH
#endif
/* Enable the MMU and caches
* lr = Resume at .Lvstart with the MMU enabled
*/
@ -619,8 +612,6 @@ __start:
ldmia r0, {r0, r1, r2, r3}
pg_l2map r0, r1, r2, r3, r4
#elif defined(CONFIG_BOOT_RUNFROMFLASH)
# error "Logic not implemented"
#else
/* Get the following value (if we did not already do so above):
*
@ -632,16 +623,16 @@ __start:
#ifdef CONFIG_IDENTITY_TEXTMAP
ldr r4, .LCvpgtable /* r4=virtual page table */
#endif
ldr r3, .LCnuttxpaddr /* r3=Aligned Nuttx start address (physical) */
ldr r3, .LCnuttxptext /* r3=Aligned Nuttx start address (physical) */
/* Now setup the page tables for our normal mapped execution region.
* We round NUTTX_START_VADDR down to the nearest megabyte boundary.
* We round NUTTX_TEXT_VADDR down to the nearest megabyte boundary.
*/
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
add r3, r3, r1 /* r3=flags + base */
add r0, r4, #(NUTTX_START_VADDR & 0xfff00000) >> 18
add r0, r4, #(NUTTX_TEXT_VADDR & 0xfff00000) >> 18
str r3, [r0], #4
/* Now map the remaining RX_NSECTIONS-1 sections of the executable
@ -660,8 +651,43 @@ __start:
* and will require a separate mapping. Or, if we are supporting on-demand
* paging of the .text region, then the RAM-based .data/.bss/heap section
* will still probably be located in a separate (virtual) address region.
*
* Here we have:
*
* R4 = The virtual address of the page table.
* R1 = MMU_MEMFLAGS
*/
#ifdef CONFIG_BOOT_RUNFROMFLASH
/* Get the following values
*
* R3 = Physical address of the NuttX RAM space (aligned to a
* one megabyte addres boundary).
*/
ldr r3, .LCnuttxpram /* r3=Aligned Nuttx RAM address (physical) */
add r3, r3, r1 /* r3=flags + base */
/* Now setup the page tables for our normal mapped execution region.
* We round NUTTX_RAM_VADDR down to the nearest megabyte boundary.
*/
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
add r0, r4, #(NUTTX_RAM_VADDR & 0xfff00000) >> 18
str r3, [r0], #4
/* Now map the remaining WR_NSECTIONS-1 sections of the RAM memory
* region.
*/
.rept WR_NSECTIONS-1
add r3, r3, #SECTION_SIZE
str r3, [r0], #4
.endr
#endif /* CONFIG_BOOT_RUNFROMFLASH */
#endif /* CONFIG_PAGING */
#endif /* CONFIG_ARCH_ROMPGTABLE */
@ -722,11 +748,14 @@ __start:
.long _ebss
.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
#if !defined(CONFIG_PAGING) && !defined(CONFIG_BOOT_RUNFROMFLASH)
.LCnuttxpaddr:
.long NUTTX_START_PADDR & 0xfff00000
#if !defined(CONFIG_PAGING)
.LCnuttxptext:
.long NUTTX_TEXT_PADDR & 0xfff00000
#ifdef CONFIG_BOOT_RUNFROMFLASH
.LCnuttxpram:
.long NUTTX_RAM_PADDR & 0xfff00000
#endif
#endif
#ifdef CONFIG_PAGING

24
arch/arm/src/sama5/chip/sama5d3x_memorymap.h
View File

@ -374,21 +374,21 @@
*
* The boot logic will create a temporarily mapping based on where NuttX is
* executing in memory. In this case, NuttX could be running from NOR FLASH,
* SDRAM, external SRAM, or internal SRAM.
* SDRAM, external SRAM, or internal SRAM. If we are running from FLASH,
* then we must have a separate mapping for the non-contiguous RAM region.
*/
#if defined(CONFIG_BOOT_RUNFROMFLASH)
# define NUTTX_START_VADDR CONFIG_SAMA5_NORFLASH_VBASE
# define NUTTX_START_PADDR CONFIG_SAMA5_NORFLASH_PBASE
#elif defined(CONFIG_BOOT_RUNFROMSDRAM)
# define NUTTX_START_VADDR SAM_DDRCS_VSECTION
# define NUTTX_START_PADDR SAM_DDRCS_PSECTION
#elif defined(CONFIG_BOOT_RUNFROMEXTSRAM)
# define NUTTX_START_VADDR CONFIG_SAMA5_SRAM_VBASE
# define NUTTX_START_PADDR CONFIG_SAMA5_SRAM_PBASE
#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */
# define NUTTX_START_VADDR SAM_ISRAM_VSECTION
# define NUTTX_START_PADDR SAM_ISRAM_PSECTION
# define NUTTX_TEXT_VADDR (CONFIG_FLASH_VSTART & 0xfff00000)
# define NUTTX_TEXT_PADDR (CONFIG_FLASH_START & 0xfff00000)
# define NUTTX_TEXT_SIZE (CONFIG_FLASH_END - NUTTX_TEXT_VADDR)
# define NUTTX_RAM_VADDR (CONFIG_RAM_VSTART & 0xfff00000)
# define NUTTX_RAM_PADDR (CONFIG_RAM_START & 0xfff00000)
# define NUTTX_RAM_SIZE (CONFIG_RAM_END - NUTTX_RAM_PADDR)
#else /* Running from some kind of RAM */
# define NUTTX_TEXT_VADDR (CONFIG_RAM_VSTART & 0xfff00000)
# define NUTTX_TEXT_PADDR (CONFIG_RAM_START & 0xfff00000)
# define NUTTX_TEXT_SIZE (CONFIG_RAM_END - NUTTX_TEXT_VADDR)
#endif
/* MMU Page Table Location

3
arch/arm/src/sama5/sam_clockconfig.c
View File

@ -445,6 +445,9 @@ void sam_clockconfig(void)
* - Enable the 32768 Hz oscillator if best accuracy is needed
* - Reprogram the SMC setup, cycle, hold, mode timing registers for EBI
* CS0, to adapt them to the new clock.
*
* Then below:
*
* - Program the PMC (Main Oscillator Enable or Bypass mode)
* - Program and Start the PLL
* - Switch the system clock to the new value

32
configs/sama5d3x-ek/README.txt
View File

@ -318,7 +318,7 @@ Writing to FLASH using SAM-BA
1. Exit the terminal emulation program and remove the USB cable from
the DBGU port (J14)
2. Connect the USB cable to the device USB port (J20)
3. JP9 must open so that (BMS == 1) to boot from on-chip Boot ROM
3. JP9 must open (BMS == 1) to boot from on-chip Boot ROM.
4. Press and maintain PB4 CS_BOOT button and power up the board. PB4
CS_BOOT button prevents booting from Nand or serial Flash by
disabling Flash Chip Selects after having powered the board, you can
@ -332,7 +332,9 @@ Writing to FLASH using SAM-BA
9. When you are finished writing to FLASH, remove the USB cable from J20
and re-connect the serial link on USB CDC / DBGU connector (J14) and
re-open the terminal emulator program.
10. Power cycle the board.
10. If you loaded code in NOR flash (CS0), then you will need to close
JP9 (BMS == 0) to force booting out of NOR flash (see NOTE).
11. Power cycle the board.
NOTES: By closing JP9 (BMS == 0), you can force the board to boot
directly to NOR FLASH. Executing from other memories will require that
@ -688,12 +690,15 @@ Configurations
CONFIG_WINDOWS_CYGWIN=y : POSIX environment under windows
CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
3. This configuration executes out of internal SRAM an can only
3. This configuration executes out of internal SRAM and can only
be loaded via JTAG.
CONFIG_SAMA5_BOOT_ISRAM=y : Boot into internal SRAM
CONFIG_BOOT_RUNFROMISRAM=y : Run from internal SRAM
STATUS:
2013-7-28: This configuration was verified functional.
ostest:
This configuration directory, performs a simple OS test using
examples/ostest.
@ -714,16 +719,17 @@ Configurations
CONFIG_WINDOWS_CYGWIN=y : POSIX environment under windows
CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
3. This configuration executes out of internal SRAM an can only
be loaded via JTAG.
3. This configuration executes out of CS0 NOR flash and can only
be loaded via JTAG. 128MB
CONFIG_SAMA5_BOOT_ISRAM=y : Boot into internal SRAM
CONFIG_BOOT_RUNFROMISRAM=y : Run from internal SRAM
CONFIG_SAMA5_BOOT_CS0FLASH=y : Boot from FLASH on CS0
CONFIG_BOOT_RUNFROMFLASH=y : Run in place on FLASH (vs copying to RAM)
CONFIG_SAMA5_EBICS0=y : Enable CS0 external memory
CONFIG_SAMA5_EBICS0_SIZE=134217728 : Memory size is 128KB
CONFIG_SAMA5_EBICS0_NOR=y : Memory type is NOR FLASH
NOTE: In order to boot in this configuration, you need to close the
BMS jumper.
STATUS:
2013-7-26: This ostest configuration is too large to fit in SAMA5
internal SRAM (along with a usable heap and a 16KB page table).
I do not want to simplify this test because I will, eventually,
need to do the entire OS test. But I will need to configure this
to run out of FLASH or SDRAM in this future. For now, I created
the smaller 'hello' configuration for the basic bringup.

2
configs/sama5d3x-ek/hello/Make.defs
View File

@ -44,7 +44,7 @@ ifeq ($(CONFIG_SAMA5_BOOT_SDRAM),y)
LDSCRIPT = ddram.ld
endif
ifeq ($(CONFIG_SAMA5_BOOT_CS0FLASH),y)
# LDSCRIPT = cs0flash.ld
LDSCRIPT = norflash.ld
endif
ifeq ($(CONFIG_SAMA5_BOOT_CS1FLASH),y)
# LDSCRIPT = cs1flash.ld

11
configs/sama5d3x-ek/include/board.h
View File

@ -217,6 +217,15 @@
#define BUTTON_USER1_BIT (1 << BUTTON_USER1)
/************************************************************************************
* Assembly Language Macros
************************************************************************************/
#ifdef __ASSEMBLY__
.macro config_sdram
.endm
#endif /* __ASSEMBLY__ */
/************************************************************************************
* Public Data
************************************************************************************/
@ -309,5 +318,5 @@ xcpt_t up_irqbutton(int id, xcpt_t irqhandler);
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* !__ASSEMBLY__ */
#endif /* __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_H */

2
configs/sama5d3x-ek/ostest/Make.defs
View File

@ -44,7 +44,7 @@ ifeq ($(CONFIG_SAMA5_BOOT_SDRAM),y)
LDSCRIPT = ddram.ld
endif
ifeq ($(CONFIG_SAMA5_BOOT_CS0FLASH),y)
# LDSCRIPT = cs0flash.ld
LDSCRIPT = norflash.ld
endif
ifeq ($(CONFIG_SAMA5_BOOT_CS1FLASH),y)
# LDSCRIPT = cs1flash.ld

32
configs/sama5d3x-ek/ostest/defconfig
View File

@ -168,15 +168,26 @@ CONFIG_SAMA5_USART1=y
# External Memory Configuration
#
# CONFIG_SAMA5_DDRCS is not set
# CONFIG_SAMA5_EBICS0 is not set
CONFIG_SAMA5_EBICS0=y
CONFIG_SAMA5_EBICS0_SIZE=134217728
# CONFIG_SAMA5_EBICS0_SRAM is not set
# CONFIG_SAMA5_EBICS0_PSRAM is not set
# CONFIG_SAMA5_EBICS0_PROM is not set
# CONFIG_SAMA5_EBICS0_EEPROM is not set
# CONFIG_SAMA5_EBICS0_EPROM is not set
# CONFIG_SAMA5_EBICS0_LCD is not set
CONFIG_SAMA5_EBICS0_NOR=y
# CONFIG_SAMA5_EBICS0_NAND is not set
# CONFIG_SAMA5_EBICS1 is not set
# CONFIG_SAMA5_EBICS2 is not set
# CONFIG_SAMA5_EBICS3 is not set
CONFIG_SAMA5_BOOT_ISRAM=y
# CONFIG_SAMA5_BOOT_ISRAM is not set
CONFIG_SAMA5_BOOT_CS0FLASH=y
#
# Heap Configuration
#
CONFIG_SAMA5_ISRAM_HEAP=y
#
# Architecture Options
@ -199,9 +210,6 @@ CONFIG_ARCH_STACKDUMP=y
#
CONFIG_BOARD_LOOPSPERMSEC=16717
# CONFIG_ARCH_CALIBRATION is not set
CONFIG_RAM_START=0x00300000
CONFIG_RAM_VSTART=0x00300000
CONFIG_RAM_SIZE=114688
CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
CONFIG_ARCH_INTERRUPTSTACK=0
@ -209,11 +217,21 @@ CONFIG_ARCH_INTERRUPTSTACK=0
# Boot options
#
# CONFIG_BOOT_RUNFROMEXTSRAM is not set
# CONFIG_BOOT_RUNFROMFLASH is not set
CONFIG_BOOT_RUNFROMISRAM=y
CONFIG_BOOT_RUNFROMFLASH=y
# CONFIG_BOOT_RUNFROMISRAM is not set
# CONFIG_BOOT_RUNFROMSDRAM is not set
# CONFIG_BOOT_COPYTORAM is not set
#
# Boot Memory Configuration
#
CONFIG_RAM_START=0x00304000
CONFIG_RAM_VSTART=0x00304000
CONFIG_RAM_SIZE=114688
CONFIG_FLASH_START=0x1000000
CONFIG_FLASH_VSTART=0x1000000
CONFIG_FLASH_SIZE=134217728
#
# Board Selection
#

2
configs/sama5d3x-ek/scripts/ddram.ld
View File

@ -91,8 +91,6 @@ SECTIONS
} > sdram
PROVIDE_HIDDEN (__exidx_end = .);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)

2
configs/sama5d3x-ek/scripts/isram.ld
View File

@ -88,8 +88,6 @@ SECTIONS
} > isram
PROVIDE_HIDDEN (__exidx_end = .);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)

127
configs/sama5d3x-ek/scripts/norflash.ld Normal file
View File

@ -0,0 +1,127 @@
/****************************************************************************
* configs/sama5d3x-ek/scripts/norflash.ld
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The SAMA5D3x-EK has 128MB of NOR flash at CS0 (0x1000:0000). In this
* configuration, the .text and a copy of the .data section will be loaded
* into NOR flash. NuttX .data, .bss, the IDLE stack, and the primary
* heap will be allocated in SRAM. The SAMA5D3 has 128 KB of ISRAM beginning
* at virtual address 0x0030:0000.
*
* Vectors in low memory are assumed to reside at the beginning of NOR flash
* 16KB of ISRAM is reserved at the beginning of ISRAM for the page table.
*/
MEMORY
{
norflash (W!RX) : ORIGIN = 0x10000000, LENGTH = 128M
isram (WRX!) : ORIGIN = 0x00304000, LENGTH = 128K - 16K
}
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(entry)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
*(.ARM.extab*)
*(.gnu.linkonce.armextab.*)
_etext = ABSOLUTE(.);
} > norflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > norflash
.ARM.extab : {
*(.ARM.extab*)
} > norflash
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > norflash
PROVIDE_HIDDEN (__exidx_end = .);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > isram AT > norflash
_eronly = LOADADDR(.data);
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > isram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

2
configs/sama5d3x-ek/scripts/pg-sram.ld
View File

@ -110,8 +110,6 @@ SECTIONS
} > isram
PROVIDE_HIDDEN (__exidx_end = .);
_eronly = ABSOLUTE(.);
.paged : {
_spaged = ABSOLUTE(.);
*(.text .text.*)

6
tools/mkconfig.c
View File

@ -184,6 +184,12 @@ int main(int argc, char **argv, char **envp)
printf("#ifndef CONFIG_RAM_END\n");
printf("# define CONFIG_RAM_END (CONFIG_RAM_START+CONFIG_RAM_SIZE)\n");
printf("#endif\n\n");
printf("/* If the end of FLASH is not specified then it is assumed to be the beginning\n");
printf(" * of FLASH plus the FLASH size.\n");
printf(" */\n\n");
printf("#ifndef CONFIG_FLASH_END\n");
printf("# define CONFIG_FLASH_END (CONFIG_FLASH_START+CONFIG_FLASH_SIZE)\n");
printf("#endif\n\n");
printf("/* If no file streams are configured, then make certain that buffered I/O\n");
printf(" * support is disabled\n");
printf(" */\n\n");