MAC driver development
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1813 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
4cc43c22e6
commit
9b3dae46ae
@ -61,6 +61,72 @@
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* Definitions
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****************************************************************************/
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/* Half duplex can be forced if CONFIG_LM3S_ETHHDUPLEX is defined. */
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#ifdef CONFIG_LM3S_ETHHDUPLEX
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# define LM3S_DUPLEX_SETBITS 0
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# define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
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#else
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# define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX
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# define LM3S_DUPLEX_CLRBITS 0
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#endif
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/* Auto CRC generation can be suppressed if CONFIG_LM3S_ETHNOAUTOCRC is definde */
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#ifdef CONFIG_LM3S_ETHNOAUTOCRC
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# define LM3S_CRC_SETBITS 0
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# define LM3S_CRC_CLRBITS MAC_TCTL_CRC
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#else
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# define LM3S_CRC_SETBITS MAC_TCTL_CRC
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# define LM3S_CRC_CLRBITS 0
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#endif
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/* Tx padding can be suppressed if CONFIG_LM3S_ETHNOPAD is defined */
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#ifdef CONFIG_LM3S_ETHNOPAD
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# define LM3S_PADEN_SETBITS 0
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# define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN
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#else
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# define LM3S_PADEN_SETBITS MAC_TCTL_PADEN
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# define LM3S_PADEN_CLRBITS 0
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#endif
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#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS)
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#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS)
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/* Multicast frames can be enabled by defining CONFIG_LM3S_MULTICAST */
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#ifdef CONFIG_LM3S_MULTICAST
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# define LM3S_AMUL_SETBITS MAC_RCTL_AMUL
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# define LM3S_AMUL_CLRBITS 0
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#else
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# define LM3S_AMUL_SETBITS 0
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# define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL
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#endif
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/* Promiscuous mode can be enabled by defining CONFIG_LM3S_PROMISCUOUS */
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#ifdef CONFIG_LM3S_PROMISCUOUS
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# define LM3S_PRMS_SETBITS MAC_RCTL_PRMS
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# define LM3S_PRMS_CLRBITS 0
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#else
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# define LM3S_PRMS_SETBITS 0
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# define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS
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#endif
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/* Bad CRC rejection can be enabled by define CONFIG_LM3S_BADCRC */
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#ifdef CONFIG_LM3S_BADCRC
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# define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC
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# define LM3S_BADCRC_CLRBITS 0
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#else
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# define LM3S_BADCRC_SETBITS 0
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# define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC
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#endif
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#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS)
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#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS)
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/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
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#define LM3S_WDDELAY (1*CLK_TCK)
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@ -151,7 +217,9 @@ static inline uint32 lm3s_ethin(struct lm3s_driver_s *priv, int offset);
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static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32 value);
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#endif
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static void lm3s_ethreset(struct lm3s_driver_s *priv);
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#if 0 /* Not used */
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static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16 value);
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#endif
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static uint16 lm3s_phyread(struct lm3s_driver_s *priv, int regaddr);
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/* Common TX logic */
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@ -216,7 +284,7 @@ static inline uint32 lm3s_ethin(struct lm3s_driver_s *priv, int offset)
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* Parameters:
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* priv - Reference to the driver state structure
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* offset - Byte offset of the register from the ethernet base address
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* value - The value to write the the Ethernet register
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* value - The value to write the Ethernet register
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*
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* Returned Value:
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* None
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@ -323,13 +391,32 @@ static void lm3s_ethreset(struct lm3s_driver_s *priv)
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*
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****************************************************************************/
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#if 0 /* Not used */
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static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16 value)
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{
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# warning "Missing Logic"
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/* Wait for any MII transactions in progress to complete */
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while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
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/* Set up the data to be written */
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DEBUGASSERT(value < MAC_MTXD_MASK);
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lm3s_ethout(priv, LM3S_MAC_MTXD_OFFSET, value);
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/* Set up the PHY register address and start the write operation */
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regaddr <<= MAC_MCTL_REGADR_SHIFT;
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DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
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lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
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/* Wait for the write transaction to complete */
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while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
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}
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#endif
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/****************************************************************************
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* Function: lm3s_phywrite
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* Function: lm3s_phyread
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*
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* Description:
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* Write a 16-bit word to a PHY register
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@ -346,8 +433,23 @@ static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16 value)
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static uint16 lm3s_phyread(struct lm3s_driver_s *priv, int regaddr)
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{
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# warning "Missing Logic"
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return 0;
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/* Wait for any MII transactions in progress to complete */
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while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
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/* Set up the PHY register address and start the read operation */
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regaddr <<= MAC_MCTL_REGADR_SHIFT;
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DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
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lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
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/* Wait for the write transaction to complete */
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while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
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/* Read and return the PHY data */
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return (uint16)(lm3s_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
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}
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/****************************************************************************
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@ -367,20 +469,85 @@ static uint16 lm3s_phyread(struct lm3s_driver_s *priv, int regaddr)
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static int lm3s_transmit(struct lm3s_driver_s *priv)
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{
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irqstate_t flags;
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uint32 regval;
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ubyte *dbuf;
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int pktlen;
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int bytesleft;
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int ret = -EBUSY;
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/* Verify that the hardware is ready to send another packet */
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#warning "Missing logic"
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/* Increment statistics */
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/* Disable Ethernet interrupts */
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flags = irqsave();
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if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
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{
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/* Increment statistics */
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/* Send the packet: address=priv->ld_dev.d_buf, length=priv->ld_dev.d_len */
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EMAC_STAT(priv, tx_packets);
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/* Restore Ethernet interrupts */
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/* Transfer the packet into the Tx FIFO. The LS 16-bits of the first
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* 32-bit word written to the Tx FIFO contains the Ethernet payload
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* data length. That is the full length of the message (d_len) minus
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* the size of the Ethernet header (14).
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*/
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/* Setup the TX timeout watchdog (perhaps restarting the timer) */
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pktlen = priv->ld_dev.d_len;
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nvdbg("Sending packet, pktlen: %d\n", pktlen);
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DEBUGASSERT(pktlen > UIP_LLH_LEN);
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(void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm3s_txtimeout, 1, (uint32)priv);
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return OK;
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dbuf = priv->ld_dev.d_buf;
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regval = (uint32)(pktlen - 4);
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regval |= ((uint32)(*dbuf++) << 16);
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regval |= ((uint32)(*dbuf++) << 24);
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lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
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/* Write all of the whole, 32-bit values in the middle of the packet */
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for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4)
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{
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/* Transfer a whole word from the user buffer. Note, the user
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* buffer may be un-aligned.
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*/
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lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32*)dbuf);
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}
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/* Write the last, partial word in the FIFO */
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if (bytesleft > 0)
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{
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/* Write the last word */
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regval = 0;
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switch (bytesleft)
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{
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case 0:
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default:
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break;
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case 3:
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regval |= ((uint32)dbuf[2] << 16);
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case 2:
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regval |= ((uint32)dbuf[1] << 8);
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case 1:
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regval |= (uint32)dbuf[0];
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break;
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}
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lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
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}
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/* Activate the transmitter */
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lm3s_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX);
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/* Setup the TX timeout watchdog (perhaps restarting the timer) */
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(void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm3s_txtimeout, 1, (uint32)priv);
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ret = OK;
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}
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irqrestore(flags);
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return ret;
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}
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/****************************************************************************
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@ -407,27 +574,29 @@ static int lm3s_transmit(struct lm3s_driver_s *priv)
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static int lm3s_uiptxpoll(struct uip_driver_s *dev)
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{
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struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
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int ret = OK;
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/* If the polling resulted in data that should be sent out on the network,
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* the field d_len is set to a value > 0.
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*/
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nvdbg("Poll result: d_len=%d\n", priv->dev.d_len);
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if (priv->ld_dev.d_len > 0)
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{
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uip_arp_out(&priv->ld_dev);
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lm3s_transmit(priv);
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/* Check if there is room in the device to hold another packet. If not,
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* return a non-zero value to terminate the poll.
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/* Send the packet. lm3s_transmit() will return zero if the
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* packet was successfully handled.
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*/
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#warning "Missing logic"
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DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
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uip_arp_out(&priv->ld_dev);
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ret =lm3s_transmit(priv);
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}
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/* If zero is returned, the polling will continue until all connections have
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* been examined.
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*/
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return 0;
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return ret;
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}
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/****************************************************************************
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@ -476,6 +645,7 @@ static void lm3s_receive(struct lm3s_driver_s *priv)
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regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
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pktlen = (int)(regval & 0x0000ffff);
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nvdbg("Receiving packet, pktlen: %d\n", pktlen);
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/* Check if the pktlen is valid. It should be large enough to
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* hold an Ethernet header and small enough to fit entirely in
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@ -512,13 +682,14 @@ static void lm3s_receive(struct lm3s_driver_s *priv)
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*dbuf++ = (ubyte)((regval >> 16) & 0xff);
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*dbuf++ = (ubyte)((regval >> 24) & 0xff);
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bytesleft = pktlen - 2;
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/* Read all of the whole, 32-bit values in the middle of the packet */
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for (; bytesleft > 3; bytesleft -= 4, dbuf += 4)
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for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4)
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{
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/* Read a whole word */
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/* Transfer a whole word to the user buffer. Note, the user
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* buffer may be un-aligned.
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*/
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*(uint32*)dbuf = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
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}
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@ -619,13 +790,20 @@ static void lm3s_receive(struct lm3s_driver_s *priv)
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static void lm3s_txdone(struct lm3s_driver_s *priv)
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{
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/* Check for errors and update statistics */
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#warning "Missing logic"
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/* If no further xmits are pending, then cancel the TX timeout */
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/* Cancel the TX timeout */
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wd_cancel(priv->ld_txtimeout);
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/* Verify that the Tx FIFO is not in use. The NEWTX bit initiates an
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* Ethernet transmission once the packet has been placed in the TX FIFO.
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* This bit is cleared once the transmission has been completed. Since
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* we get here because of of TXEMP which indicates that the packet was
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* transmitted and that the TX FIFO is empty, NEWTX should always be zero
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* at this point.
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*/
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DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
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/* Then poll uIP for new XMIT data */
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(void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
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@ -741,10 +919,15 @@ static void lm3s_txtimeout(int argc, uint32 arg, ...)
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/* Increment statistics and dump debug info */
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ndbg("Tx timeout\n");
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EMAC_STAT(priv, tx_timeouts);
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/* Then reset the hardware */
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DEBUGASSERT(priv->ld_bifup);
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lm3s_ifdown(&priv->ld_dev);
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lm3s_ifup(&priv->ld_dev);
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/* Then poll uIP for new XMIT data */
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(void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
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@ -771,16 +954,24 @@ static void lm3s_polltimer(int argc, uint32 arg, ...)
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{
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struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg;
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/* Check if there is room in the send another Tx packet. */
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#warning "Missing logic"
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/* Check if we can send another Tx packet now. The NEWTX bit initiates an
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* Ethernet transmission once the packet has been placed in the TX FIFO.
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* This bit is cleared once the transmission has been completed.
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*
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* NOTE: This can cause missing poll cycles and, hence, some timing
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* inaccuracies.
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*/
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/* If so, update TCP timing states and poll uIP for new XMIT data */
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if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
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{
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/* If so, update TCP timing states and poll uIP for new XMIT data */
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(void)uip_timer(&priv->ld_dev, lm3s_uiptxpoll, LM3S_POLLHSEC);
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(void)uip_timer(&priv->ld_dev, lm3s_uiptxpoll, LM3S_POLLHSEC);
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/* Setup the watchdog poll timer again */
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/* Setup the watchdog poll timer again */
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(void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, arg);
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(void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, arg);
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}
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}
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/****************************************************************************
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@ -837,19 +1028,19 @@ static int lm3s_ifup(struct uip_driver_s *dev)
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* TX Padding Enabled).
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*/
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# warning "These should be configurable items"
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regval = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET);
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regval |= (MAC_TCTL_DUPLEX|MAC_TCTL_CRC|MAC_TCTL_PADEN);
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regval &= ~LM3S_TCTCL_CLRBITS;
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regval |= LM3S_TCTCL_SETBITS;
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lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
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nvdbg("TCTL: %08x\n", regval);
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/* Setup the receive control register (Disable multicast frames, disable
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* promiscuous mode, disable bad CRC rejection). >>> These should be configurable items <<<
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* promiscuous mode, disable bad CRC rejection).
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*/
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# warning "These should be configurable items"
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regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
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regval &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL);
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regval &= ~LM3S_RCTCL_CLRBITS;
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regval |= LM3S_RCTCL_SETBITS;
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lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
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nvdbg("RCTL: %08x\n", regval);
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@ -866,9 +1057,11 @@ static int lm3s_ifup(struct uip_driver_s *dev)
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nvdbg("TS: %08x\n", regval);
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#endif
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/* Wait for the link to come up */
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# warning "This should use a semaphore and an interrupt"
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/* Wait for the link to come up. This following is not very conservative
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* of system resources -- it really should wait gracefully on a semaphore
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* and the interrupt handler should post the semaphore when LINKSTATUS is
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* set
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*/
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ndbg("Waiting for link\n");
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do
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@ -960,6 +1153,10 @@ static int lm3s_ifdown(struct uip_driver_s *dev)
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irqstate_t flags;
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uint32 regval;
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ndbg("Taking down: %d.%d.%d.%d\n",
|
||||
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
|
||||
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
|
||||
|
||||
/* Cancel the TX poll timer and TX timeout timers */
|
||||
|
||||
flags = irqsave();
|
||||
@ -1040,16 +1237,20 @@ static int lm3s_txavail(struct uip_driver_s *dev)
|
||||
struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
|
||||
irqstate_t flags;
|
||||
|
||||
/* Ignore the notification if the interface is not yet up or if the Tx FIFO
|
||||
* hardware is not available at this time. The NEWTX bit initiates an
|
||||
* Ethernet transmission once the packet has been placed in the TX FIFO.
|
||||
* This bit is cleared once the transmission has been completed. When the
|
||||
* transmission completes, lm3s_txdone() will be called and the Tx polling
|
||||
* will occur at that time.
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
/* Ignore the notification if the interface is not yet up */
|
||||
|
||||
if (priv->ld_bifup)
|
||||
if (priv->ld_bifup && (lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
{
|
||||
/* Check if there is room in the hardware to hold another outgoing packet. */
|
||||
#warning "Missing logic"
|
||||
|
||||
/* If so, then poll uIP for new XMIT data */
|
||||
/* If the interface is up and we can use the Tx FIFO, then poll uIP
|
||||
* for new Tx data
|
||||
*/
|
||||
|
||||
(void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
|
||||
}
|
||||
@ -1089,6 +1290,8 @@ static inline int lm3s_initialize(int intf)
|
||||
|
||||
/* Check if the Ethernet module is present */
|
||||
|
||||
ndbg("Setting up eth%d\n", intf);
|
||||
|
||||
#if LMS_NETHCONTROLLERS > 1
|
||||
# error "This debug check only works with one interface"
|
||||
#else
|
||||
|
||||
@ -171,6 +171,14 @@
|
||||
|
||||
#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */
|
||||
|
||||
/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */
|
||||
|
||||
#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */
|
||||
|
||||
/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */
|
||||
|
||||
#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */
|
||||
|
||||
/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
|
||||
|
||||
#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */
|
||||
|
||||
@ -955,7 +955,7 @@ static int ez80emac_transmit(struct ez80emac_driver_s *priv)
|
||||
flags = irqsave();
|
||||
EMAC_STAT(priv, tx_packets);
|
||||
|
||||
/* The current packet to be sent is txnetx; Calculate the new txnext and
|
||||
/* The current packet to be sent is txnext; Calculate the new txnext and
|
||||
* set the ownership to host so that the EMAC does not try to transmit
|
||||
* the next packet.
|
||||
*
|
||||
@ -967,10 +967,10 @@ static int ez80emac_transmit(struct ez80emac_driver_s *priv)
|
||||
*/
|
||||
|
||||
txdesc = priv->txnext;
|
||||
|
||||
|
||||
len = EMAC_PKTBUF_ALIGN(priv->dev.d_len + SIZEOF_EMACSDESC);
|
||||
txnext = (FAR struct ez80emac_desc_s *)((ubyte*)txdesc + len);
|
||||
|
||||
|
||||
/* Handle wraparound to the beginning of the TX region */
|
||||
|
||||
if ((ubyte*)txnext + SIZEOF_EMACSDESC >= (ubyte*)priv->rxstart)
|
||||
@ -1070,6 +1070,10 @@ static int ez80emac_uiptxpoll(struct uip_driver_s *dev)
|
||||
nvdbg("Poll result: d_len=%d\n", priv->dev.d_len);
|
||||
if (priv->dev.d_len > 0)
|
||||
{
|
||||
/* Send the packet. ez80emac_transmit() will return zero if the
|
||||
* packet was successfully handled.
|
||||
*/
|
||||
|
||||
uip_arp_out(&priv->dev);
|
||||
ret = ez80emac_transmit(priv);
|
||||
}
|
||||
|
||||
@ -205,6 +205,12 @@ Eagle100-specific Configuration Options
|
||||
CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
|
||||
CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
|
||||
a MAC address (via lm3s_ethernetmac()), then this should be selected.
|
||||
CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
|
||||
CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
|
||||
CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
|
||||
CONFIG_LM3S_MULTICAST - Set to enable multicast frames
|
||||
CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode
|
||||
CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection.
|
||||
|
||||
Configurations
|
||||
^^^^^^^^^^^^^^
|
||||
|
||||
@ -136,10 +136,22 @@ CONFIG_SPI2_DISABLE=y
|
||||
# CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
|
||||
# CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
|
||||
# a MAC address (via lm3s_ethernetmac()), then this should be selected.
|
||||
|
||||
# CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
|
||||
# CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
|
||||
# CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
|
||||
# CONFIG_LM3S_MULTICAST - Set to enable multicast frames
|
||||
# CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode
|
||||
# CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection.
|
||||
#
|
||||
CONFIG_LM3S_ETHERNET=y
|
||||
CONFIG_LM3S_ETHLEDS=n
|
||||
CONFIG_LM3S_BOARDMAC=y
|
||||
CONFIG_LM3S_ETHHDUPLEX=n
|
||||
CONFIG_LM3S_ETHNOAUTOCRC=n
|
||||
CONFIG_LM3S_ETHNOPAD=n
|
||||
CONFIG_LM3S_MULTICAST=n
|
||||
CONFIG_LM3S_PROMISCUOUS=n
|
||||
CONFIG_LM3S_BADCRC=n
|
||||
|
||||
#
|
||||
# General build options
|
||||
|
||||
@ -131,8 +131,27 @@ CONFIG_SPI2_DISABLE=y
|
||||
#
|
||||
# LM3S6918 specific serial device driver settings
|
||||
#
|
||||
# CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET)
|
||||
# to build the LM3S Ethernet driver
|
||||
# CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
|
||||
# CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
|
||||
# a MAC address (via lm3s_ethernetmac()), then this should be selected.
|
||||
# CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
|
||||
# CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
|
||||
# CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
|
||||
# CONFIG_LM3S_MULTICAST - Set to enable multicast frames
|
||||
# CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode
|
||||
# CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection.
|
||||
#
|
||||
CONFIG_LM3S_ETHERNET=n
|
||||
CONFIG_LM3S_ETHLEDS=n
|
||||
CONFIG_LM3S_BOARDMAC=y
|
||||
CONFIG_LM3S_ETHHDUPLEX=n
|
||||
CONFIG_LM3S_ETHNOAUTOCRC=n
|
||||
CONFIG_LM3S_ETHNOPAD=n
|
||||
CONFIG_LM3S_MULTICAST=n
|
||||
CONFIG_LM3S_PROMISCUOUS=n
|
||||
CONFIG_LM3S_BADCRC=n
|
||||
|
||||
#
|
||||
# General build options
|
||||
|
||||
@ -131,8 +131,27 @@ CONFIG_SPI2_DISABLE=y
|
||||
#
|
||||
# LM3S6918 specific serial device driver settings
|
||||
#
|
||||
# CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET)
|
||||
# to build the LM3S Ethernet driver
|
||||
# CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
|
||||
# CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
|
||||
# a MAC address (via lm3s_ethernetmac()), then this should be selected.
|
||||
# CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
|
||||
# CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
|
||||
# CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
|
||||
# CONFIG_LM3S_MULTICAST - Set to enable multicast frames
|
||||
# CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode
|
||||
# CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection.
|
||||
#
|
||||
CONFIG_LM3S_ETHERNET=n
|
||||
CONFIG_LM3S_ETHLEDS=n
|
||||
CONFIG_LM3S_BOARDMAC=y
|
||||
CONFIG_LM3S_ETHHDUPLEX=n
|
||||
CONFIG_LM3S_ETHNOAUTOCRC=n
|
||||
CONFIG_LM3S_ETHNOPAD=n
|
||||
CONFIG_LM3S_MULTICAST=n
|
||||
CONFIG_LM3S_PROMISCUOUS=n
|
||||
CONFIG_LM3S_BADCRC=n
|
||||
|
||||
#
|
||||
# General build options
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user