riscv/barrier: Define more granular memory barriers

Separate barriers for full (memory + I/O) and local memory (cache) flushing.
This commit is contained in:
Ville Juven 2023-06-14 14:19:29 +03:00 committed by Alan Carvalho de Assis
parent f2690837e7
commit 9b5746cb5f
8 changed files with 22 additions and 15 deletions

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@ -21,12 +21,20 @@
#ifndef __ARCH_RISCV_INCLUDE_BARRIERS_H #ifndef __ARCH_RISCV_INCLUDE_BARRIERS_H
#define __ARCH_RISCV_INCLUDE_BARRIERS_H #define __ARCH_RISCV_INCLUDE_BARRIERS_H
/* Common memory barriers: /* Common memory barriers (p=predecessor, s=successor) */
* __DMB() is used to synchronize external devices (I/O domain mainly)
* __ISB() is used to synchronize the instruction and data streams
*/
#define __DMB() __asm__ __volatile__ ("fence" ::: "memory") #define __FENCE(p, s) __asm__ __volatile__ ("fence "#p", "#s ::: "memory")
#define __ISB() __asm__ __volatile__ ("fence.i" ::: "memory")
/* __DMB() is used to flush local data caches (memory) */
#define __DMB() __FENCE(rw, rw)
/* __MB() is a full memory barrier */
#define __MB() __FENCE(iorw, iorw)
/* __ISB() is used to synchronize the instruction and data streams */
#define __ISB() __asm__ __volatile__ ("fence.i" ::: "memory")
#endif /* __ARCH_RISCV_INCLUDE_BARRIERS_H */ #endif /* __ARCH_RISCV_INCLUDE_BARRIERS_H */

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@ -736,10 +736,8 @@ int up_addrenv_select(const arch_addrenv_t *addrenv)
int up_addrenv_coherent(const arch_addrenv_t *addrenv) int up_addrenv_coherent(const arch_addrenv_t *addrenv)
{ {
/* Flush the instruction and data caches */ /* Nothing needs to be done */
__ISB();
__DMB();
return OK; return OK;
} }

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@ -187,7 +187,8 @@ static inline void mmu_write_satp(uintptr_t reg)
( (
"csrw satp, %0\n" "csrw satp, %0\n"
"sfence.vma x0, x0\n" "sfence.vma x0, x0\n"
"fence\n" "fence rw, rw\n"
"fence.i\n"
: :
: "rK" (reg) : "rK" (reg)
: "memory" : "memory"

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@ -124,7 +124,7 @@ static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv,
/* Make sure it sticks */ /* Make sure it sticks */
__DMB(); __MB();
} }
#else #else
static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv) static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)

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@ -147,7 +147,7 @@ void riscv_percpu_add_hart(uintptr_t hartid)
/* Make sure it sticks */ /* Make sure it sticks */
__DMB(); __MB();
} }
/**************************************************************************** /****************************************************************************

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@ -100,7 +100,7 @@ static struct gpio_callback_s g_mss_gpio_callbacks[GPIO_BANK0_NUM_PINS +
static void mpfs_gpio_irq_clear(int bank, int pin) static void mpfs_gpio_irq_clear(int bank, int pin)
{ {
putreg32(1 << pin, g_gpio_base[bank] + MPFS_GPIO_INTR_OFFSET); putreg32(1 << pin, g_gpio_base[bank] + MPFS_GPIO_INTR_OFFSET);
__DMB(); __MB();
} }
/**************************************************************************** /****************************************************************************

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@ -81,5 +81,5 @@ void sbi_mscratch_assign(uintptr_t hartid)
/* Make sure mscratch is updated before continuing */ /* Make sure mscratch is updated before continuing */
__DMB(); __MB();
} }

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@ -96,5 +96,5 @@ void sbi_set_mtimecmp(uint64_t value)
/* Make sure it sticks */ /* Make sure it sticks */
__DMB(); __MB();
} }