riscv/barrier: Define more granular memory barriers
Separate barriers for full (memory + I/O) and local memory (cache) flushing.
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@ -21,12 +21,20 @@
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#ifndef __ARCH_RISCV_INCLUDE_BARRIERS_H
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#ifndef __ARCH_RISCV_INCLUDE_BARRIERS_H
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#define __ARCH_RISCV_INCLUDE_BARRIERS_H
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#define __ARCH_RISCV_INCLUDE_BARRIERS_H
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/* Common memory barriers:
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/* Common memory barriers (p=predecessor, s=successor) */
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* __DMB() is used to synchronize external devices (I/O domain mainly)
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* __ISB() is used to synchronize the instruction and data streams
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*/
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#define __DMB() __asm__ __volatile__ ("fence" ::: "memory")
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#define __FENCE(p, s) __asm__ __volatile__ ("fence "#p", "#s ::: "memory")
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#define __ISB() __asm__ __volatile__ ("fence.i" ::: "memory")
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/* __DMB() is used to flush local data caches (memory) */
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#define __DMB() __FENCE(rw, rw)
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/* __MB() is a full memory barrier */
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#define __MB() __FENCE(iorw, iorw)
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/* __ISB() is used to synchronize the instruction and data streams */
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#define __ISB() __asm__ __volatile__ ("fence.i" ::: "memory")
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#endif /* __ARCH_RISCV_INCLUDE_BARRIERS_H */
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#endif /* __ARCH_RISCV_INCLUDE_BARRIERS_H */
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@ -736,10 +736,8 @@ int up_addrenv_select(const arch_addrenv_t *addrenv)
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int up_addrenv_coherent(const arch_addrenv_t *addrenv)
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int up_addrenv_coherent(const arch_addrenv_t *addrenv)
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{
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{
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/* Flush the instruction and data caches */
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/* Nothing needs to be done */
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__ISB();
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__DMB();
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return OK;
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return OK;
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}
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}
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@ -187,7 +187,8 @@ static inline void mmu_write_satp(uintptr_t reg)
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(
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(
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"csrw satp, %0\n"
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"csrw satp, %0\n"
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"sfence.vma x0, x0\n"
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"sfence.vma x0, x0\n"
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"fence\n"
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"fence rw, rw\n"
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"fence.i\n"
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:
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:
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: "rK" (reg)
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: "rK" (reg)
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: "memory"
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: "memory"
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@ -124,7 +124,7 @@ static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv,
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/* Make sure it sticks */
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/* Make sure it sticks */
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__DMB();
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__MB();
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}
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}
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#else
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#else
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static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
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static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
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@ -147,7 +147,7 @@ void riscv_percpu_add_hart(uintptr_t hartid)
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/* Make sure it sticks */
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/* Make sure it sticks */
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__DMB();
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__MB();
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}
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}
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/****************************************************************************
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/****************************************************************************
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@ -100,7 +100,7 @@ static struct gpio_callback_s g_mss_gpio_callbacks[GPIO_BANK0_NUM_PINS +
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static void mpfs_gpio_irq_clear(int bank, int pin)
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static void mpfs_gpio_irq_clear(int bank, int pin)
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{
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{
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putreg32(1 << pin, g_gpio_base[bank] + MPFS_GPIO_INTR_OFFSET);
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putreg32(1 << pin, g_gpio_base[bank] + MPFS_GPIO_INTR_OFFSET);
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__DMB();
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__MB();
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}
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}
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/****************************************************************************
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/****************************************************************************
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@ -81,5 +81,5 @@ void sbi_mscratch_assign(uintptr_t hartid)
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/* Make sure mscratch is updated before continuing */
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/* Make sure mscratch is updated before continuing */
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__DMB();
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__MB();
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}
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}
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@ -96,5 +96,5 @@ void sbi_set_mtimecmp(uint64_t value)
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/* Make sure it sticks */
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/* Make sure it sticks */
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__DMB();
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__MB();
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}
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}
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