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arch/arm64: move sgi attach and enable to gic init

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Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
This commit is contained in:
zhangyuan21 2023-05-06 19:28:56 +08:00 committed by Alan Carvalho de Assis
parent f8b5fd2a9a
commit 9b882b46be
6 changed files with 12 additions and 20 deletions
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2
arch/arm64/src/common/arm64_cpupause.c
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@ -272,7 +272,7 @@ int up_cpu_pause(int cpu)
/* Execute SGI2 */ /* Execute SGI2 */
ret = arm64_gic_raise_sgi(SGI_CPU_PAUSE, (1 << cpu)); ret = arm64_gic_raise_sgi(GIC_IRQ_SGI2, (1 << cpu));
if (ret < 0) if (ret < 0)
{ {
/* What happened? Unlock the g_cpu_wait spinlock */ /* What happened? Unlock the g_cpu_wait spinlock */

9
arch/arm64/src/common/arm64_cpustart.c
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@ -258,8 +258,6 @@ void arm64_boot_secondary_c_routine(void)
up_perf_init(NULL); up_perf_init(NULL);
up_enable_irq(SGI_CPU_PAUSE);
func = cpu_boot_params.func; func = cpu_boot_params.func;
arg = cpu_boot_params.arg; arg = cpu_boot_params.arg;
ARM64_DSB(); ARM64_DSB();
@ -277,10 +275,3 @@ void arm64_boot_secondary_c_routine(void)
func(arg); func(arg);
} }
int arm64_smp_sgi_init(void)
{
irq_attach(SGI_CPU_PAUSE, arm64_pause_handler, 0);
up_enable_irq(SGI_CPU_PAUSE);
return 0;
}

4
arch/arm64/src/common/arm64_doirq.c
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@ -128,10 +128,6 @@ void up_irqinitialize(void)
arm64_gic_initialize(); /* Initialization common to all CPUs */ arm64_gic_initialize(); /* Initialization common to all CPUs */
#ifdef CONFIG_SMP
arm64_smp_sgi_init();
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS #ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */ /* And finally, enable interrupts */

4
arch/arm64/src/common/arm64_gic.h
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@ -311,8 +311,6 @@ int arm64_gic_raise_sgi(unsigned int sgi_id, uint16_t target_list);
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
#define SGI_CPU_PAUSE GIC_IRQ_SGI0
/**************************************************************************** /****************************************************************************
* Name: arm64_pause_handler * Name: arm64_pause_handler
* *
@ -337,8 +335,6 @@ int arm64_pause_handler(int irq, void *context, void *arg);
void arm64_gic_secondary_init(void); void arm64_gic_secondary_init(void);
int arm64_smp_sgi_init(void);
#endif #endif
#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H */ #endif /* __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H */

3
arch/arm64/src/common/arm64_gicv2.c
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@ -819,8 +819,7 @@ static void arm_gic0_initialize(void)
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
/* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */ /* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */
DEBUGVERIFY(irq_attach(GIC_IRQ_SGI1, arm_start_handler, NULL)); DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm64_pause_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm_pause_handler, NULL));
#endif #endif
} }

10
arch/arm64/src/common/arm64_gicv3.c
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@ -554,6 +554,12 @@ static void gicv3_dist_init(void)
putreg32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS), putreg32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS),
GICD_CTLR); GICD_CTLR);
#endif #endif
#ifdef CONFIG_SMP
/* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */
DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm64_pause_handler, NULL));
#endif
} }
void up_enable_irq(int irq) void up_enable_irq(int irq)
@ -790,6 +796,10 @@ static void arm64_gic_init(void)
gicv3_rdist_enable(gic_get_rdist()); gicv3_rdist_enable(gic_get_rdist());
gicv3_cpuif_init(); gicv3_cpuif_init();
#ifdef CONFIG_SMP
up_enable_irq(GIC_IRQ_SGI2);
#endif
} }
int arm64_gic_initialize(void) int arm64_gic_initialize(void)