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riscv/riscv_exception.c: Print the EPC value always

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The value printed by assert() cannot always be trusted to be correct,
as it relies on the stack / stack pointer not being corrupt.

The CPU register always points to the faulting instruction so print it
out in the exception handler.
This commit is contained in:
Ville Juven 2023-01-23 13:45:43 +02:00 committed by Xiang Xiao
parent 8bf693b362
commit 9b88f8ea5c
1 changed files with 3 additions and 2 deletions
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5
arch/risc-v/src/common/riscv_exception.c
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@ -74,9 +74,10 @@ int riscv_exception(int mcause, void *regs, void *args)
{ {
uintptr_t cause = mcause & RISCV_IRQ_MASK; uintptr_t cause = mcause & RISCV_IRQ_MASK;
_alert("EXCEPTION: %s. MCAUSE: %" PRIxREG ", MTVAL: %" PRIxREG "\n", _alert("EXCEPTION: %s. MCAUSE: %" PRIxREG ", EPC: %" PRIxREG
", MTVAL: %" PRIxREG "\n",
mcause > RISCV_MAX_EXCEPTION ? "Unknown" : g_reasons_str[cause], mcause > RISCV_MAX_EXCEPTION ? "Unknown" : g_reasons_str[cause],
cause, READ_CSR(CSR_TVAL)); cause, READ_CSR(CSR_EPC), READ_CSR(CSR_TVAL));
_alert("PANIC!!! Exception = %" PRIxREG "\n", cause); _alert("PANIC!!! Exception = %" PRIxREG "\n", cause);
up_irq_save(); up_irq_save();