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TMS570 is big-endian

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This commit is contained in:
Gregory Nutt 2015-12-26 14:47:54 -06:00
parent 1f2d9c9174
commit 9bcf27d15b
3 changed files with 21 additions and 2 deletions
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1
arch/arm/Kconfig
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@ -237,6 +237,7 @@ config ARCH_CHIP_STR71X
config ARCH_CHIP_TMS570 config ARCH_CHIP_TMS570
bool "TI TMS570" bool "TI TMS570"
select ENDIAN_BIG
select ARCH_HAVE_LOWVECTORS select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_RAMFUNCS
select ARMV7R_MEMINIT select ARMV7R_MEMINIT

11
arch/arm/src/armv7-a/arm_head.S
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@ -410,7 +410,7 @@ __start:
* replacement strategy. * replacement strategy.
* SCTLR_HA Bit 17: Not supported by A5 * SCTLR_HA Bit 17: Not supported by A5
* *
* SCTLR_EE Bit 25: Little endian (reset value). * SCTLR_EE Bit 25: 0=Little endian (reset value).
* SCTLR_TRE Bit 28: No memory region remapping (reset value) * SCTLR_TRE Bit 28: No memory region remapping (reset value)
* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value). * SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
* SCTLR_TE Bit 30: All exceptions handled in ARM state (reset value). * SCTLR_TE Bit 30: All exceptions handled in ARM state (reset value).
@ -477,6 +477,15 @@ __start:
orr r0, r0, #(SCTLR_A) orr r0, r0, #(SCTLR_A)
#endif #endif
#ifdef CONFIG_ENDIAN_BIG
/* Big endian mode
*
* SCTLR_EE Bit 25: 1=Big endian.
*/
orr r0, r0, #(SCTLR_EE)
#endif
#ifdef CPU_AFE_ENABLE #ifdef CPU_AFE_ENABLE
/* AP[0:2] Permissions model /* AP[0:2] Permissions model
* *

11
arch/arm/src/armv7-r/arm_head.S
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@ -217,7 +217,7 @@ __start:
* SCTLR_U Bit 22: Unaligned access model (always one) * SCTLR_U Bit 22: Unaligned access model (always one)
* *
* SCTLR_VE Bit 24: Interrupt Vectors Enable bit * SCTLR_VE Bit 24: Interrupt Vectors Enable bit
* SCTLR_EE Bit 25: Little endian. * SCTLR_EE Bit 25: 0=Little endian.
* SCTLR_NMFI Bit 27: Non-maskable FIQ (NMFI) support * SCTLR_NMFI Bit 27: Non-maskable FIQ (NMFI) support
* SCTLR_TE Bit 30: All exceptions handled in ARM state. * SCTLR_TE Bit 30: All exceptions handled in ARM state.
* SCTLR_IE Bit 31: Instruction endian-ness. * SCTLR_IE Bit 31: Instruction endian-ness.
@ -322,6 +322,15 @@ __start:
orr r0, r0, #(SCTLR_VE) orr r0, r0, #(SCTLR_VE)
#endif #endif
#ifdef CONFIG_ENDIAN_BIG
/* Big endian mode
*
* SCTLR_EE Bit 25: 1=Big endian.
*/
orr r0, r0, #(SCTLR_EE)
#endif
#ifdef CPU_NONMASKABLE_FIQ #ifdef CPU_NONMASKABLE_FIQ
/* Non-maskable FIQ support /* Non-maskable FIQ support
* *