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armv7-a/gicv2: move IRQ to group1 and group0 as the FIQ

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Purpose: make the the os crash when busyloop with interrupt disable

Follow the arm gicv2 spec, if we want to use the IRQ and FIQ
simultaneously when not using the processor Security Externsions.
We should:
1. IRQ to Group 1 and FIQ to Group 0;
2. Set CICC_CTLR.FIQEn to 1;

Then in NuttX:
1. implement the arm_decodefiq and directly crash in it;
2. provide interface to change the IRQ to FIQ, e.g. change the
   watchdog IRQ to FIQ, so the watchdog can trigger even with the
   interrupt disabled (up_irq_save() called);

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
This commit is contained in:
zhangyuan21 2023-06-27 10:40:06 +08:00 committed by Masayuki Ishikawa
parent d4d49e9645
commit 9c0d2e1a3c
18 changed files with 211 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/include/armv7-a/irq.h
View File

@ -357,9 +357,10 @@ noinstrument_function static inline irqstate_t up_irq_save(void)
__asm__ __volatile__
(
"\tmrs %0, cpsr\n"
"\tcpsid i\n"
#if defined(CONFIG_ARMV7A_DECODEFIQ)
#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
"\tcpsid f\n"
#else
"\tcpsid i\n"
#endif
: "=r" (cpsr)
:
@ -378,9 +379,11 @@ static inline irqstate_t up_irq_enable(void)
__asm__ __volatile__
(
"\tmrs %0, cpsr\n"
"\tcpsie i\n"
#if defined(CONFIG_ARMV7A_DECODEFIQ)
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
"\tcpsie f\n"
#endif
#ifndef CONFIG_ARCH_TRUSTZONE_SECURE
"\tcpsie i\n"
#endif
: "=r" (cpsr)
:

4
arch/arm/src/armv7-a/CMakeLists.txt
View File

@ -119,4 +119,8 @@ if(CONFIG_ARCH_HAVE_PSCI)
list(APPEND SRCS arm_cpu_psci.c arm_smccc.S)
endif()
if(CONFIG_ARCH_HIPRI_INTERRUPT)
list(APPEND SRCS arm_dofiq.c)
endif()
target_sources(arch PRIVATE ${SRCS})

10
arch/arm/src/armv7-a/Kconfig
View File

@ -8,6 +8,8 @@ comment "ARMv7-A Configuration Options"
config ARMV7A_HAVE_GICv2
bool
select ARCH_HAVE_IRQTRIGGER
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_HIPRI_INTERRUPT
default n
---help---
Selected by the configuration tool if the architecture supports the
@ -173,14 +175,6 @@ endif # ARCH_L2CACHE
endmenu # L2 Cache Configuration
endif # ARMV7A_HAVE_L2CC
config ARMV7A_DECODEFIQ
bool "FIQ Handler"
default n
---help---
Select this option if your platform supports the function
arm_decodefiq(). This is used primarily to support secure TrustZone
interrupts received on the FIQ vector.
config ARMV7A_ALIGNMENT_TRAP
bool "Enable Alignment Check at __start"
default n

4
arch/arm/src/armv7-a/Make.defs
View File

@ -98,3 +98,7 @@ ifeq ($(CONFIG_ARCH_HAVE_PSCI),y)
CMN_ASRCS += arm_smccc.S
CMN_CSRCS += arm_cpu_psci.c
endif
ifeq ($(CONFIG_ARCH_HIPRI_INTERRUPT),y)
CMN_CSRCS += arm_dofiq.c
endif

63
arch/arm/src/armv7-a/arm_dofiq.c Normal file
View File

@ -0,0 +1,63 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_dofiq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "gic.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_dofiq
*
* Description:
* Receives the decoded GIC interrupt information and dispatches control
* to the attached fiq handler. It is not allowed to call OS functions
* within a FIQ handler.
*
****************************************************************************/
uint32_t *arm_dofiq(int fiq, uint32_t *regs)
{
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
irq_dispatch(fiq, regs);
#endif
board_autoled_off(LED_INIRQ);
return regs;
}

75
arch/arm/src/armv7-a/arm_gicv2.c
View File

@ -41,7 +41,7 @@
* Public Functions
****************************************************************************/
#ifdef CONFIG_ARCH_HAVE_TRUSTZONE
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
/****************************************************************************
* Name: up_set_secure_irq
*
@ -120,8 +120,8 @@ void arm_gic0_initialize(void)
/* A processor in Secure State sets:
*
* 1. Which interrupts are non-secure (ICDISR). All set to zero (group
* 0).
* 1. Which interrupts are non-secure (ICDISR). All set to one (group
* 1).
* 2. Trigger mode of the SPI (ICDICFR). All fields set to 0b01->Level
* sensitive, 1-N model.
* 3. Interrupt Clear-Enable (ICDICER)
@ -137,7 +137,7 @@ void arm_gic0_initialize(void)
for (irq = GIC_IRQ_SPI; irq < nlines; irq += 32)
{
putreg32(0x00000000, GIC_ICDISR(irq)); /* SPIs group 0 */
putreg32(0xffffffff, GIC_ICDISR(irq)); /* SPIs group 1 */
putreg32(0xffffffff, GIC_ICDICER(irq)); /* SPIs disabled */
}
@ -205,7 +205,7 @@ void arm_gic_initialize(void)
putreg32(0x000000ff, GIC_ICDISR(0));
#else
putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */
putreg32(0xffffffff, GIC_ICDISR(0)); /* SGIs and PPIs no-secure */
#endif
putreg32(0xfe000000, GIC_ICDICER(0)); /* PPIs disabled */
@ -224,12 +224,17 @@ void arm_gic_initialize(void)
* field; the value n (n=0-6) specifies that bits (n+1) through bit 7 are
* used in the comparison for interrupt pre-emption. A GIC supports a
* minimum of 16 and a maximum of 256 priority levels so not all binary
* point settings may be meaningul. The special value n=7
* (GIC_ICCBPR_NOPREMPT) disables pre-emption. We disable all pre-emption
* here to prevent nesting of interrupt handling.
* point settings may be meaningul. When CONFIG_ARCH_HIPRI_INTERRUPT is not
* enabled, we set n=7 (GIC_ICCBPR_NOPREMPT) to disable interrupt nesting.
* When CONFIG_ARCH_HIPRI_INTERRUPT is enabled, we set n=6 (GIC_ICCBPR_7_7)
* (g.sssssss) to support group priority.
*/
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
putreg32(GIC_ICCBPR_7_7, GIC_ICCBPR);
#else
putreg32(GIC_ICCBPR_NOPREMPT, GIC_ICCBPR);
#endif
/* Program the idle priority in the PMR */
@ -239,7 +244,12 @@ void arm_gic_initialize(void)
iccicr = getreg32(GIC_ICCICR);
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
#ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE
/* Clear non-secure state ICCICR bits to be configured below */
iccicr &= ~(GIC_ICCICRU_EOIMODENS | GIC_ICCICRU_ENABLEGRP1 |
GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_IRQBYPDISGRP1);
#else
/* Clear secure state ICCICR bits to be configured below */
iccicr &= ~(GIC_ICCICRS_FIQEN | GIC_ICCICRS_ACKTCTL | GIC_ICCICRS_CBPR |
@ -247,16 +257,9 @@ void arm_gic_initialize(void)
GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 |
GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 |
GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1);
#else
/* Clear non-secure state ICCICR bits to be configured below */
iccicr &= ~(GIC_ICCICRU_EOIMODENS | GIC_ICCICRU_ENABLEGRP1 |
GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_IRQBYPDISGRP1);
#endif
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
/* Set FIQn=1 if secure interrupts are to signal using nfiq_c.
*
* NOTE: Only for processors that operate in secure state.
@ -284,7 +287,17 @@ void arm_gic_initialize(void)
# endif
#endif
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
#ifndef CONFIG_ARCH_TRUSTZONE_SECURE
iccicr |= GIC_ICCICRS_ACKTCTL;
#endif
#ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE
/* Enable the Group 1 interrupts and disable Group 1 bypass. */
iccicr |= (GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 |
GIC_ICCICRU_IRQBYPDISGRP1);
icddcr = GIC_ICDDCR_ENABLE;
#else
/* Enable the Group 0 interrupts, FIQEn and disable Group 0/1
* bypass.
*/
@ -293,14 +306,6 @@ void arm_gic_initialize(void)
GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 |
GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1);
icddcr = (GIC_ICDDCR_ENABLEGRP0 | GIC_ICDDCR_ENABLEGRP1);
#else
/* Enable the Group 1 interrupts and disable Group 1 bypass. */
iccicr |= (GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 |
GIC_ICCICRU_IRQBYPDISGRP1);
icddcr = GIC_ICDDCR_ENABLE;
#endif
/* Write the final ICCICR value to enable the GIC. */
@ -381,6 +386,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
*
****************************************************************************/
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
uint32_t *arm_decodefiq(uint32_t *regs)
{
uint32_t regval;
@ -391,9 +397,9 @@ uint32_t *arm_decodefiq(uint32_t *regs)
regval = getreg32(GIC_ICCIAR);
irq = (regval & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT;
#ifdef CONFIG_ARMV7A_GIC_EOIMODE
# ifdef CONFIG_ARMV7A_GIC_EOIMODE
putreg32(regval, GIC_ICCEOIR);
#endif
# endif
/* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending
* interrupt.
@ -405,18 +411,23 @@ uint32_t *arm_decodefiq(uint32_t *regs)
{
/* Dispatch the interrupt */
# ifdef CONFIG_ARCH_HIPRI_INTERRUPT
regs = arm_dofiq(irq, regs);
# else
regs = arm_doirq(irq, regs);
# endif
}
/* Write to the end-of-interrupt register */
#ifdef CONFIG_ARMV7A_GIC_EOIMODE
# ifdef CONFIG_ARMV7A_GIC_EOIMODE
putreg32(regval, GIC_ICCDIR);
#else
# else
putreg32(regval, GIC_ICCEOIR);
#endif
# endif
return regs;
}
#endif
/****************************************************************************
* Name: up_enable_irq
@ -500,6 +511,8 @@ void up_disable_irq(int irq)
*
* Description:
* Set the priority of an IRQ.
* For group0, priority bit[7] must be 0;
* For group1, priority bit[7] must be 1;
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.

11
arch/arm/src/armv7-a/arm_initialstate.c
View File

@ -137,15 +137,14 @@ void up_initial_state(struct tcb_s *tcb)
cpsr |= (PSR_I_BIT | PSR_F_BIT);
#else /* CONFIG_SUPPRESS_INTERRUPTS */
/* Leave IRQs enabled (Also FIQs if CONFIG_ARMV7A_DECODEFIQ is selected) */
#ifndef CONFIG_ARMV7A_DECODEFIQ
#elif !defined(CONFIG_ARCH_TRUSTZONE_SECURE) && !defined(CONFIG_ARCH_HIPRI_INTERRUPT)
/* Leave IRQs enabled (Also FIQs if CONFIG_ARCH_TRUSTZONE_SECURE or
* CONFIG_ARCH_HIPRI_INTERRUPT is selected)
*/
cpsr |= PSR_F_BIT;
#endif /* !CONFIG_ARMV7A_DECODEFIQ */
#endif /* CONFIG_SUPPRESS_INTERRUPTS */
#endif
#ifdef CONFIG_ARM_THUMB
cpsr |= PSR_T_BIT;

24
arch/arm/src/armv7-a/arm_vectors.S
View File

@ -180,10 +180,10 @@ arm_vectorirq:
/* Switch to SYS mode */
#ifdef CONFIG_ARMV7A_DECODEFIQ
cpsid if, #PSR_MODE_SYS
#else
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
cpsid i, #PSR_MODE_SYS
#else
cpsid if, #PSR_MODE_SYS
#endif
/* Create a context structure. First set aside a stack frame
@ -290,10 +290,10 @@ arm_vectorsvc:
/* Switch to SYS mode */
#ifdef CONFIG_ARMV7A_DECODEFIQ
cpsid if, #PSR_MODE_SYS
#else
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
cpsid i, #PSR_MODE_SYS
#else
cpsid if, #PSR_MODE_SYS
#endif
/* Create a context structure. First set aside a stack frame
@ -401,10 +401,10 @@ arm_vectordata:
/* Switch to SYS mode */
#ifdef CONFIG_ARMV7A_DECODEFIQ
cpsid if, #PSR_MODE_SYS
#else
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
cpsid i, #PSR_MODE_SYS
#else
cpsid if, #PSR_MODE_SYS
#endif
/* Create a context structure. First set aside a stack frame
@ -642,14 +642,14 @@ arm_vectorundefinsn:
*
****************************************************************************/
#ifdef CONFIG_ARMV7A_DECODEFIQ
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
.globl arm_decodefiq
#endif
.globl arm_vectorfiq
.type arm_vectorfiq, %function
arm_vectorfiq:
#ifdef CONFIG_ARMV7A_DECODEFIQ
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
/* Save the LR and SPSR onto the SYS mode stack before switch. */
@ -771,7 +771,7 @@ g_intstacktop:
* Name: g_fiqstackalloc/g_fiqstacktop
****************************************************************************/
#ifdef CONFIG_ARMV7A_DECODEFIQ
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
.globl g_fiqstackalloc
.type g_fiqstackalloc, object
.globl g_fiqstacktop

54
arch/arm/src/armv7-a/gic.h
View File

@ -93,6 +93,11 @@
#define GIC_SHIFT32(n) ((n) & 31) /* Shift 1-bit per field */
#define GIC_MASK32(n) (1 << GIC_SHIFT32(n)) /* 1-bit mask */
/* GIC group */
#define GIC_GROUP0 0
#define GIC_GROUP1 1
/* GIC Register Offsets *****************************************************/
/* CPU Interface registers */
@ -537,7 +542,11 @@
#define GIC_ICDSGIR_INTID_MASK (0x3ff << GIC_ICDSGIR_INTID_SHIFT)
# define GIC_ICDSGIR_INTID(n) ((uint32_t)(n) << GIC_ICDSGIR_INTID_SHIFT)
/* Bits 10-14: Reserved */
#define GIC_ICDSGIR_NSATT (1 << 15)
#define GIC_ICDSGIR_NSATT_SHIFT (15)
#define GIC_ICDSGIR_NSATT_MASK (1 << GIC_ICDSGIR_NSATT_SHIFT)
# define GIC_ICDSGIR_NSATT_GRP0 (0 << GIC_ICDSGIR_NSATT_SHIFT)
# define GIC_ICDSGIR_NSATT_GRP1 (1 << GIC_ICDSGIR_NSATT_SHIFT)
#define GIC_ICDSGIR_CPUTARGET_SHIFT (16) /* Bits 16-23: CPU target */
#define GIC_ICDSGIR_CPUTARGET_MASK (0xff << GIC_ICDSGIR_CPUTARGET_SHIFT)
# define GIC_ICDSGIR_CPUTARGET(n) ((uint32_t)(n) << GIC_ICDSGIR_CPUTARGET_SHIFT)
@ -671,6 +680,15 @@ static inline void arm_cpu_sgi(int sgi, unsigned int cpuset)
GIC_ICDSGIR_TGTFILTER_THIS;
#endif
#ifndef CONFIG_ARCH_TRUSTZONE_SECURE
/* Set NSATT be 1: forward the SGI specified in the SGIINTID field to a
* specified CPU interfaces only if the SGI is configured as Group 1 on
* that interface.
*/
regval |= GIC_ICDSGIR_NSATT_GRP1;
#endif
putreg32(regval, GIC_ICDSGIR);
}
@ -757,6 +775,38 @@ int arm_gic_irq_trigger(int irq, bool edge);
uint32_t *arm_decodeirq(uint32_t *regs);
/****************************************************************************
* Name: arm_dofiq
*
* Description:
* Receives the decoded GIC interrupt information and dispatches control
* to the attached fiq handler.
*
****************************************************************************/
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
uint32_t *arm_dofiq(int irq, uint32_t *regs);
#endif
/****************************************************************************
* Name: arm_decodefiq
*
* Description:
* This function is called from the FIQ vector handler in arm_vectors.S.
* At this point, the interrupt has been taken and the registers have
* been saved on the stack. This function simply needs to determine the
* the fiq number of the interrupt and then to call arm_doirq to dispatch
* the interrupt.
*
* Input Parameters:
* regs - A pointer to the register save area on the stack.
*
****************************************************************************/
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
uint32_t *arm_decodefiq(uint32_t *regs);
#endif
/****************************************************************************
* Name: arm_start_handler
*
@ -820,7 +870,7 @@ int arm_pause_handler(int irq, void *context, void *arg);
#ifdef CONFIG_DEBUG_IRQ_INFO
void arm_gic_dump(const char *msg, bool all, int irq);
#else
# define arm_gic_dump(m,a,i)
# define arm_gic_dump(msg, all, irq)
#endif
#undef EXTERN

2
arch/arm/src/armv7-r/arm_gicv2.c
View File

@ -41,7 +41,7 @@
* Public Functions
****************************************************************************/
#ifdef CONFIG_ARCH_HAVE_TRUSTZONE
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
/****************************************************************************
* Name: up_set_secure_irq
*

2
arch/arm/src/armv8-m/arm_doirq.c
View File

@ -68,7 +68,7 @@ static inline bool arm_from_thread(uint32_t excret)
return true;
}
#ifdef CONFIG_ARCH_HAVE_TRUSTZONE
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
if (!(excret & EXC_RETURN_SECURE_STACK) &&
(excret & EXC_RETURN_EXC_SECURE))
{

2
arch/arm/src/armv8-m/arm_secure_irq.c
View File

@ -33,7 +33,7 @@
#include "arm_internal.h"
#include "nvic.h"
#ifdef CONFIG_ARCH_HAVE_TRUSTZONE
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
/****************************************************************************
* Public Functions

6
arch/arm/src/common/arm_internal.h
View File

@ -402,6 +402,12 @@ int arm_securefault(int irq, void *context, void *arg);
#elif defined(CONFIG_ARCH_ARMV7A) || defined(CONFIG_ARCH_ARMV7R) || defined(CONFIG_ARCH_ARMV8R)
/* Interrupt acknowledge and dispatch */
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
uint32_t *arm_dofiq(int fiq, uint32_t *regs);
#endif
/* Paging support */
#ifdef CONFIG_LEGACY_PAGING

1
arch/arm/src/sama5/Kconfig
View File

@ -491,7 +491,6 @@ config SAMA5_SAIC
bool "Secure Advanced Interrupt Controller (SAIC)"
default n
depends on SAMA5_HAVE_SAIC
select ARMV7A_DECODEFIQ
config SAMA5_RXLP
bool "Low power asynchronous receiver"

7
arch/arm/src/sama5/sam_irq.c
View File

@ -617,11 +617,11 @@ uint32_t *arm_decodeirq(uint32_t *regs)
return sam_decodeirq(SAM_AIC_VBASE, regs);
}
#if defined(CONFIG_SAMA5_SAIC)
/* This is the entry point from the ARM FIQ vector handler */
uint32_t *arm_decodefiq(uint32_t *regs)
{
#if defined(CONFIG_SAMA5_SAIC)
uint32_t *ret;
/* In order to distinguish a FIQ from a true secure interrupt we need to
@ -646,8 +646,11 @@ uint32_t *arm_decodefiq(uint32_t *regs)
}
return ret;
}
#else
DEBUGASSERT(false);
return NULL;
#endif
}
/****************************************************************************
* Name: up_disable_irq (and sam_disable_irq helper)

2
arch/arm64/src/common/arm64_gicv2.c
View File

@ -647,7 +647,7 @@ static inline unsigned int arm_gic_nlines(void)
return (field + 1) << 5;
}
#ifdef CONFIG_ARCH_HAVE_TRUSTZONE
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
/****************************************************************************
* Name: up_set_secure_irq
*

1
boards/arm/nrf91/nrf9160-dk/configs/modem_ns/defconfig
View File

@ -17,6 +17,7 @@ CONFIG_ARCH_CHIP_NRF9160=y
CONFIG_ARCH_CHIP_NRF91=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_STDARG_H=y
CONFIG_ARCH_TRUSTZONE_NONSECURE=y
CONFIG_ARMV8M_CMSE=y
CONFIG_BOARD_LOOPSPERMSEC=5500
CONFIG_BUILTIN=y

4
include/nuttx/arch.h
View File

@ -1659,7 +1659,7 @@ int up_prioritize_irq(int irq, int priority);
*
****************************************************************************/
#ifdef CONFIG_ARCH_HAVE_TRUSTZONE
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
void up_secure_irq(int irq, bool secure);
#else
# define up_secure_irq(i, s)
@ -1685,7 +1685,7 @@ void up_send_smp_call(cpu_set_t cpuset);
*
****************************************************************************/
#ifdef CONFIG_ARCH_HAVE_TRUSTZONE
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT)
void up_secure_irq_all(bool secure);
#else
# define up_secure_irq_all(s)