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armv7m/v8m:Restore the CSSELR state before setting.

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Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
This commit is contained in:
chenrun1 2023-06-23 23:52:06 +08:00 committed by Xiang Xiao
parent 823c3b32e7
commit 9c2bc0edbe
4 changed files with 30 additions and 16 deletions
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6
arch/arm/src/armv7-a/cp15_cacheops.c
View File

@ -52,9 +52,7 @@ static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways,
csselr = CP15_GET(CSSELR);
csselr = (csselr & ~0x01) | (icache & 0x01);
CP15_SET(CSSELR, csselr);
CP15_SET(CSSELR, (csselr & ~0x01) | (icache & 0x01));
ccsidr = CP15_GET(CCSIDR);
@ -68,6 +66,8 @@ static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways,
*ways = ((ccsidr >> 3) & 0x3ff) + 1;
}
CP15_SET(CSSELR, csselr); /* restore csselr */
return (1 << ((ccsidr & 0x7) + 2)) * 4;
}

17
arch/arm/src/armv7-m/arm_cache.c
View File

@ -129,17 +129,20 @@ static size_t up_get_cache_linesize(bool icache)
if (icache)
{
csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_ICACHE;
putreg32((csselr & ~NVIC_CSSELR_IND) |
NVIC_CSSELR_IND_ICACHE, NVIC_CSSELR);
}
else
{
csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_DCACHE;
putreg32((csselr & ~NVIC_CSSELR_IND) |
NVIC_CSSELR_IND_DCACHE, NVIC_CSSELR);
}
putreg32(csselr, NVIC_CSSELR);
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
putreg32(csselr, NVIC_CSSELR); /* restore csselr */
return 1 << sshift;
}
@ -170,11 +173,13 @@ static size_t up_get_cache_size(bool icache)
if (icache)
{
csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_ICACHE;
putreg32((csselr & ~NVIC_CSSELR_IND) |
NVIC_CSSELR_IND_ICACHE, NVIC_CSSELR);
}
else
{
csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_DCACHE;
putreg32((csselr & ~NVIC_CSSELR_IND) |
NVIC_CSSELR_IND_DCACHE, NVIC_CSSELR);
}
ccsidr = getreg32(NVIC_CCSIDR);
@ -183,6 +188,8 @@ static size_t up_get_cache_size(bool icache)
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
line = 1 << sshift;
putreg32(csselr, NVIC_CSSELR); /* restore csselr */
return sets * ways * line;
}
#endif

6
arch/arm/src/armv7-r/cp15_cacheops.c
View File

@ -52,9 +52,7 @@ static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways,
csselr = CP15_GET(CSSELR);
csselr = (csselr & ~0x01) | (icache & 0x01);
CP15_SET(CSSELR, csselr);
CP15_SET(CSSELR, (csselr & ~0x01) | (icache & 0x01));
ccsidr = CP15_GET(CCSIDR);
@ -68,6 +66,8 @@ static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways,
*ways = ((ccsidr >> 3) & 0x3ff) + 1;
}
CP15_SET(CSSELR, csselr); /* restore csselr */
return (1 << ((ccsidr & 0x7) + 2)) * 4;
}

17
arch/arm/src/armv8-m/arm_cache.c
View File

@ -129,17 +129,20 @@ static size_t up_get_cache_linesize(bool icache)
if (icache)
{
csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_ICACHE;
putreg32((csselr & ~NVIC_CSSELR_IND) |
NVIC_CSSELR_IND_ICACHE, NVIC_CSSELR);
}
else
{
csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_DCACHE;
putreg32((csselr & ~NVIC_CSSELR_IND) |
NVIC_CSSELR_IND_DCACHE, NVIC_CSSELR);
}
putreg32(csselr, NVIC_CSSELR);
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
putreg32(csselr, NVIC_CSSELR); /* restore csselr */
return 1 << sshift;
}
@ -170,11 +173,13 @@ static size_t up_get_cache_size(bool icache)
if (icache)
{
csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_ICACHE;
putreg32((csselr & ~NVIC_CSSELR_IND) |
NVIC_CSSELR_IND_ICACHE, NVIC_CSSELR);
}
else
{
csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_DCACHE;
putreg32((csselr & ~NVIC_CSSELR_IND) |
NVIC_CSSELR_IND_DCACHE, NVIC_CSSELR);
}
ccsidr = getreg32(NVIC_CCSIDR);
@ -183,6 +188,8 @@ static size_t up_get_cache_size(bool icache)
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
line = 1 << sshift;
putreg32(csselr, NVIC_CSSELR); /* restore csselr */
return sets * ways * line;
}
#endif