arch/arm/src/stm32f0l0: Bring in missing RCC file. Now there are two files implementing stm32_clockonfig(). Yech. ./setenv.sh Also fixes several compile issues. The STM32L0 boards now compile and link without error.
This commit is contained in:
Gregory Nutt
parent
33a4ec969a
commit
9c5d0003aa
@ -309,7 +309,6 @@ config ARCH_CHIP_STM32F0
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config ARCH_CHIP_STM32L0
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bool "STMicro STM32 L0"
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select ARCH_CORTEXM0
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depends on EXPERIMENTAL
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---help---
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STMicro STM32L0 architectures (ARM Cortex-M0).
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@ -65,16 +65,18 @@ CMN_CSRCS += up_dumpnvic.c
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endif
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CHIP_ASRCS =
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CHIP_CSRCS = stm32_clockconfig.c stm32_gpio.c stm32_irq.c # stm32_dma_v1.c
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CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c stm32_start.c
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CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_irq.c # stm32_dma_v1.c
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CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c
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# Configuration-dependent STM32F0/L0 files
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ifdef ($(CONFIG_ARCH_CHIP_STM32L0),y
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CHIP_CSRCS += stm32l0_rcc.c
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ifeq ($(CONFIG_ARCH_CHIP_STM32F0),y)
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CHIP_CSRCS += stm32_clockconfig.c
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else ifeq ($(CONFIG_ARCH_CHIP_STM32L0),y)
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CHIP_CSRCS += stm32_rcc.c
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endif
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ifdef ($(CONFIG_STM32F0L0_PWR),y
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ifeq ($(CONFIG_STM32F0L0_PWR),y)
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CHIP_CSRCS += stm32_pwr.c
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endif
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@ -48,6 +48,9 @@
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* Pre-processor Definitions
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************************************************************************************/
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#undef HAVE_PWR_WKUP2 1
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#undef HAVE_PWR_WKUP3 1
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/* Register Offsets *****************************************************************/
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#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */
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@ -47,6 +47,9 @@
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* Pre-processor Definitions
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************************************************************************************/
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#define HAVE_PWR_WKUP2 1
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#define HAVE_PWR_WKUP3 1
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/* Register Offsets *****************************************************************/
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#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */
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@ -245,7 +245,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
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*
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****************************************************************************/
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#ifdef CONFIG_STM32_DMACAPABLE
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#ifdef CONFIG_STM32F0L0_DMACAPABLE
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bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
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#else
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# define stm32_dmacapable(maddr, count, ccr) (true)
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@ -55,20 +55,7 @@
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* Private Data
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************************************************************************************/
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/* Wakeup Pin Definitions: See chip/stm32_pwr.h */
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#undef HAVE_PWR_WKUP2
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#undef HAVE_PWR_WKUP3
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#if defined(CONFIG_STM32_STM32F30XX)
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# define HAVE_PWR_WKUP2 1
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#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F33XX) || \
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defined(CONFIG_STM32_STM32F37XX)
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# define HAVE_PWR_WKUP2 1
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# define HAVE_PWR_WKUP3 1
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#endif
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/* Thr parts only support a single Wake-up pin do not include the numeric suffix
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/* Parts only support a single Wake-up pin do not include the numeric suffix
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* in the naming.
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*/
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@ -323,7 +310,7 @@ bool stm32_pwr_getwuf(void)
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*
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************************************************************************************/
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#ifdef CONFIG_STM32_ENERGYLITE
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#ifdef CONFIG_STM32F0L0_ENERGYLITE
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void stm32_pwr_setvos(uint16_t vos)
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{
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uint16_t regval;
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@ -336,7 +323,7 @@ void stm32_pwr_setvos(uint16_t vos)
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* 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.
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*/
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while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
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while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0)
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{
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}
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@ -414,6 +401,6 @@ void stm32_pwr_disablepvd(void)
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stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0);
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}
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#endif /* CONFIG_STM32_ENERGYLITE */
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#endif /* CONFIG_STM32F0L0_ENERGYLITE */
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#endif /* CONFIG_STM32F0L0_PWR */
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@ -33,8 +33,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
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#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
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#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H
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#define __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H
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/************************************************************************************
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* Included Files
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@ -181,7 +181,7 @@ bool stm32_pwr_getwuf(void);
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*
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************************************************************************************/
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#ifdef CONFIG_STM32_ENERGYLITE
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#ifdef CONFIG_STM32F0L0_ENERGYLITE
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void stm32_pwr_setvos(uint16_t vos);
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/************************************************************************************
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@ -223,7 +223,7 @@ void stm32_pwr_enablepvd(void);
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void stm32_pwr_disablepvd(void);
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#endif /* CONFIG_STM32_ENERGYLITE */
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#endif /* CONFIG_STM32F0L0_ENERGYLITE */
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#undef EXTERN
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#if defined(__cplusplus)
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@ -231,4 +231,4 @@ void stm32_pwr_disablepvd(void);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H */
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#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H */
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227
arch/arm/src/stm32f0l0/stm32_rcc.c
Normal file
227
arch/arm/src/stm32f0l0/stm32_rcc.c
Normal file
@ -0,0 +1,227 @@
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/****************************************************************************
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* arch/arm/src/stm32f0l0/stm32_rcc.c
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <assert.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "hardware/stm32_flash.h"
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#include "hardware/stm32_rcc.h"
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#include "stm32_gpio.h"
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#include "stm32_clockconfig.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Allow up to 100 milliseconds for the high speed clock to become ready.
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* that is a very long delay, but if the clock does not become ready we are
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* hosed anyway.
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*/
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#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/* Include chip-specific clocking initialization logic */
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#if defined(CONFIG_ARCH_CHIP_STM32L0)
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# include "stm32l0_rcc.c"
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#else
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# error "Unsupported STM32F0/L0 RCC"
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: rcc_resetbkp
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*
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* Description:
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* The RTC needs to reset the Backup Domain to change RTCSEL and resetting
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* the Backup Domain renders to disabling the LSE as consequence. In order
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* to avoid resetting the Backup Domain when we already configured LSE we
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* will reset the Backup Domain early (here).
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#if defined(CONFIG_STM32F0L0_RTC) && defined(CONFIG_STM32F0L0_PWR)
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static inline void rcc_resetbkp(void)
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{
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uint32_t regval;
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/* Check if the RTC is already configured */
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stm32_pwr_initbkp(false);
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regval = getreg32(RTC_MAGIC_REG);
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if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET)
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{
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stm32_pwr_enablebkp(true);
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/* We might be changing RTCSEL - to ensure such changes work, we must
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* reset the backup domain (having backed up the RTC_MAGIC token)
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*/
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modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
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modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
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stm32_pwr_enablebkp(false);
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}
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}
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#else
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# define rcc_resetbkp()
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_clockconfig
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*
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* Description:
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* Called to establish the clock settings based on the values in board.h.
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* This function (by default) will reset most everything, enable the PLL,
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* and enable peripheral clocking for all peripherals enabled in the NuttX
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* configuration file.
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*
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* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
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* will be enabled by an externally provided, board-specific function called
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* stm32_board_clockconfig().
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void stm32_clockconfig(void)
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{
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/* Make sure that we are starting in the reset state */
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rcc_reset();
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/* Reset backup domain if appropriate */
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rcc_resetbkp();
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#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
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/* Invoke Board Custom Clock Configuration */
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stm32_board_clockconfig();
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#else
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/* Invoke standard, fixed clock configuration based on definitions in board.h */
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stm32_stdclockconfig();
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#endif
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#ifdef CONFIG_STM32F0L0_SYSCFG_IOCOMPENSATION
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/* Enable I/O Compensation */
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stm32_iocompensation();
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#endif
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/* Enable peripheral clocking */
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rcc_enableperipherals();
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}
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/************************************************************************************
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* Name: stm32_clockenable
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*
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* Description:
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* Re-enable the clock and restore the clock settings based on settings in board.h.
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* This function is only available to support low-power modes of operation: When
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* re-awakening from deep-sleep modes, it is necessary to re-enable/re-start the
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* PLL
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*
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* This functional performs a subset of the operations performed by
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* stm32_clockconfig(): It does not reset any devices, and it does not reset the
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* currenlty enabled peripheral clocks.
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*
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* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will
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* be enabled by an externally provided, board-specific function called
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* stm32_board_clockconfig().
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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#ifdef CONFIG_PM
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void stm32_clockenable(void)
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{
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#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
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/* Invoke Board Custom Clock Configuration */
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stm32_board_clockconfig();
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#else
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/* Invoke standard, fixed clock configuration based on definitions in board.h */
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stm32_stdclockconfig();
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#endif
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}
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#endif
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@ -37,6 +37,8 @@
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* Included Files
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****************************************************************************/
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#include "stm32_pwr.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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